Development of vacuum underfill technology for a 3D chip stack

Sakuma, Katsuyuki; Kohara, Sayuri; Sueoka, Kuniaki; Orii, Yasumitsu; Kawakami, Mikio; Asai, Kazuo; Hirayama, Y.; Knickerbocker, John

doi:10.1088/0960-1317/21/3/035024

Cited by 17 publications

(6 citation statements)

References 12 publications

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“…10). In contrast to the traditional capillary underfill process in which the flow of underfill is driven by the surface tension, a vacuum filling approach was developed by researchers at IBM [18,55]. In the vacuum filling approach, the flow of underfill is driven by the pressure difference, and this change in the dispensing mechanism led to better filling quality.…”

Section: Issues On Underfillmentioning

confidence: 99%

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Liu

Park

2014

Journal of Electronic Packaging

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Three-dimensional (3D) packaging with through-silicon-vias (TSVs) is an emerging technology featuring smaller package size, higher interconnection density, and better performance; 2.5D packaging using silicon interposers with TSVs is an incremental step toward 3D packaging. Formation of TSVs and interconnection between chips and/or wafers are two key enabling technologies for 3D and 2.5D packaging, and different interconnection methods in chip-to-chip, chip-to-wafer, and wafer-to-wafer schemes have been developed. This article reviews state-of-the-art interconnection technologies reported in recent technical papers. Issues such as bump formation, assembly/bonding process, as well as underfill dispensing in each interconnection type are discussed.

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Section: Issues On Underfillmentioning

confidence: 99%

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Liu

Park

2014

Journal of Electronic Packaging

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“…Post-applied methods [14][15][16][17][18][19] develop on the basis of process and typically utilize dispensing or molding technique to underfill an assembled package. A dominant benefit for post-applied methods is entirely compatibility with current existing SMT facilities.…”

Section: Introductionmentioning

confidence: 99%

“…A dominant benefit for post-applied methods is entirely compatibility with current existing SMT facilities. A vacuum capillary underfill (VCUF) introduced by IBM [14,15] employs a low-volatile material to underfill a 3D chip stack. VCUF can be considered as an evolvement of the 2D conventional underfill since the material is dispensed along chip edges in a vacuum-assisted dispensing system.…”

Section: Introductionmentioning

confidence: 99%

3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

Le¹,

Lee²,

Zhang³

2017

J. Micromech. Microeng.

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3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer), vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger-dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point-source to provide fluid for each layer. The free dots form a capillary flow to fill the under-chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller ‘keep-out’ area occupation on the substrate.

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“…Sakuma et al, while investigating alternate methods of incorporating undefills into packages, have discussed formulation of higher thermal conductivity underfills [4]. Integration of liquid cooling into the package structure has also been investigated by Brunschwiler [5], although the impact of integrating liquid into the packages needs further study.…”

Section: Introductionmentioning

confidence: 99%

An efficient lid design for cooling stacked flip-chip 3D packages

Sikka

Wakil

Toy

et al. 2012

13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems

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3D chip-stack packages are more difficult to cool than 2D chip packages due to additional thermal resistances in the heat flow path. The additional thermal resistances are due to the presence of the C4 joins between the chips, the BEOL wiring layers in each chip and the silicon thickness of the chips in the stack. In this paper we present an efficient lid design for a 3D flip-chip package that allows contact, through a thin thermal interface material (TIM) layer, of exposed chip regions of the lower chips in the 3D vertical stack.The efficient lid was assembled on to 3D thermal test vehicle packages and its thermal advantage over standard lid 3D packages was experimentally demonstrated. The packages were cross-sectioned to ensure that the assembly process yielded the correct TIM gaps. A thermal conduction model was calibrated to the experimental data and the stacked chipchip and the efficient lid TIM thermal resistances were extracted from the model. A sensitivity analysis was then conducted to identify the important parameters controlling the thermal performance of the 3D package.

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Development of vacuum underfill technology for a 3D chip stack

Cited by 17 publications

References 12 publications

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

An efficient lid design for cooling stacked flip-chip 3D packages

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