Characterization of stacked die using die-to-wafer integration for high yield and throughput

Abstract

We have developed a die-to-wafer integration technology for high yield and throughput for the formation of high bandwidth, high performance, and short-distance interconnections in three-dimensional (3D) stack applications. The results show that multiple 70-µm thick die can be successfully assembled in stacks on top of a wafer using a single bonding step, rather than by repeated sequential bonding steps. In this study, 1-die, 3-die, and 6-die stacks were assembled and the electrical resistance of link chains consisting of through-silicon-vias (TSVs), low-volume leadfree interconnects, and Cu wiring links was measured. The average resistance of the TSV including the lead-free interconnect was as low as 21 mΩ. The stacking throughput can be dramatically improved by this die-to-wafer integration technology and the contact resistance and reliability test results suggest that a reliable integration technology can be used for 3D stack applications. IntroductionSemiconductor devices have realized improvements in performance with high speed, increased functionality, low power dissipation, and low cost by continuing their remarkable miniaturization and high degree of integration per Moore's Law. However, with further miniaturization to 32 nm and smaller, problems such as increasing costs of capital investment and research and development, as well as technical problems such as increasing transistor leakage current mean that continued miniaturization at historical rates of development is becoming difficult. To address such problems, 3D integrated multiple circuits are considered to be a promising solution. This is because 3D integration technology should make it possible to improve performance by stacking chips with 32 nm features rather than simply shrinking the device dimensions.There are several different approaches for 3D integration, including die-to-die, die-to-wafer, and wafer-to-wafer. Since actual implementations have been emphasized, die-to-die approaches have taken the lead in development. Technologies in which dies are directly connected to other dies by using vertical interconnects have been proposed and several different processes for making TSVs and low-volume leadfree solder interconnects have been studied [1][2][3][4][5][6]. Each die is aligned and stacked by using high-precision flip chip bonding. Die-to-die integration provides higher flexibility and higher yield, since it's possible to sort known good die (KGD) before stacking. However, low fabrication throughput

Bonding technologies for chip level and wafer level 3D integration

“…In this study, we used the CALM process [6] to improve throughput for chip level integration. We fabricated chip stacks to evaluate alignment accuracy and thermal reliability characteristics of the CALM process.…”

“…Generally, one by one sequential die assembly is slower and more expensive than batch assembly process, however die pick and place of multiple die can aide productivity. The authors previously reported CALM, in which cavities were used as stacking templates for chips on a wafer [6]. CALM has good potential for effective, inexpensive, and high throughput 3D fabrication.…”

Effect of joint shape controlled by thermocompression bonding on the reliability performance of 60цm-pitch solder micro bump interconnections

“…Three-dimensional integration circuit (3DIC) has become a very promising technology in the semiconductor industry, recently [1][2][3][4][5]. By introducing the structure of through silicon via (TSV) inside the die, vertically multiple-die stack would be practicable.…”

Effects of UBM structure/material on the reliability performance of 3D chip stacking with 30μm-pitch solder micro bump interconnections

“…This technology provides advantages of short interconnections, simple routing, reduced stray capacitances, miniaturization, and compact packaging. Due to the rapid development of 3DIC packaging, high density and fine pitch micro bumps technology has become the important topic in microelectronics industry [1][2][3][4][5]. However, fine pitch flip chip bonding has many challenges and issues in terms of package assembly process and package reliability performance.…”