Advanced inspection technique for deep-submicron and high-aspect-ratio contact holes

Matsui, Miyako; Nozoe, Mari; Arauchi, Keiko; Takafuji, A.; Nishiyama, Hidetoshi; Goto, Yasushi

doi:10.1117/1.1585062

Cited by 8 publications

(8 citation statements)

References 7 publications

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“…An electron-beam (EB) inspection method has the capability to detect such small defects, which at present may be optically invisible. In addition, using an EB inspection system, we have already developed a technique to detect electrical defects such as incomplete contact failure [2]. This technique uses voltage contrasts of SEM images, which are formed by the charges on a device pattern due to the electron irradiation from the EB.…”

Section: Introductionmentioning

confidence: 99%

Dielectric-thickness dependence of damage induced by electron-beam irradiation of MNOS gate pattern

et al. 2007

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We analyzed the electron-irradiation damage induced by electron-beam inspection of MNOS capacitors with various gate-dielectric thicknesses. Damage induced in a MNOS capacitor with SiON dielectric for high-performance CMOS devices was compared with that induced on a MOS capacitor with SiO 2 dielectric. We found that there is no remarkable difference between the damage to MOS capacitors and that to MNOS capacitors. The induced damage strongly depends on the thickness of the gate dielectric. Damages were induced when a higher-energy electron-beam, whose electron range was larger than the thickness of the gate electrode, was irradiated. When the electron beam was irradiated to a MOS capacitor with gate-dielectric thickness of 10.0 nm the flat-band-voltage shifted due to the created traps. When the electron beam was scanned to a MOS or MNOS capacitor with gate-dielectric thickness of 4.0 nm, V fb shifted by less than 6 mV. However, the leakage-current density increased to 10 -7 A/cm 2 at gate-electrode voltage of 3.0 V. On the other hand, when the electron beam was scanned on a MNOS capacitor with 2.5-nm-thick SiON dielectric, even the leakage current density was not increased. Accordingly, for damage-free inspection when gate-dielectric thickness is 4.0 nm or more, the electron-beam energy should be lower so that the electron range is smaller than the thickness of the gate electrode.

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Section: Introductionmentioning

confidence: 99%

Dielectric-thickness dependence of damage induced by electron-beam irradiation of MNOS gate pattern

et al. 2007

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“…For this reason, scanning electron microscopy (SEM) inspection systems offering high-resolution imaging and the ability to evaluate electrical properties have been developed. [2][3][4][5][6] However, charge-up remains a challenging issue. The electron beam induces the accumulation of positive or negative charge on the wafer, with significant influences on subsequent inspection.…”

Section: Introductionmentioning

confidence: 99%

Robust and efficient image processing scheme for electron beam LSI wafer pattern inspection

Hiroi¹,

Fukunishi²

2004

Metrology, Inspection, and Process Control for Microlithography XVIII

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Electron beam-based wafer pattern inspection systems have the major advantage of allowing for the inspection of internal electric properties. However, charge-up of the wafer resulting from the use of an electron beam significantly influences inspection and remains a challenging issue. As an alternative approach to strict charge control, the authors propose a new inspection method that is capable of error-free, one-time inspection for recipe preparation, and which provides high-efficiency defect review and low error ratio inspection. Inspection is carried out at a higher-than-expected sensitivity, and defect candidate images are stored by a defect image analyzer (DIA). After inspection, the stored information contains both actual defects and nuisance defects. The distribution of candidate defects is displayed on a wafer map and the operator reviews the stored images and high-resolution review images on demand in order to check whether defects are true or nuisance defects. If necessary, the operator then adjusts the detection sensitivity and the system re-judges the stored data, displaying the modified wafer map to screen. In this way, the proposed system is robust against sensitivity drift caused by charge-up, and offers efficient, low error ratio inspection.

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“…In particular, we have already reported that the gray scale of such SEM images depends on the variation of defect resistance due to an incomplete contact. [2][3][4][5] The prospective process flow by applying our in-line inspection resistance mapping using an SEM inspection system is shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

Quantitative measurement of voltage contrast in scanning electron microscope images for in-line resistance inspection of wafers

Matsui

Odaka

Nagaishi

et al. 2010

J. Micro/Nanolith. MEMS MOEMS

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We develope an in-line inspection method for partial-electrical measurement of defect resistance, which is quantitatively estimated from the voltage contrast formed in a scanning electron microscopy (SEM) image of an incomplete-contact defect. We first manufacture standard calibration wafers for the voltage-contrast calibration. The contact resistance of systematically formed defects varied from 10 8 to 10 17 . Then, we quantitatively analyze the gray scales of these defect images captured using a review SEM. As a result, calibration curves for estimating the contact resistance of the incomplete-contact defect are obtained at a probe current of 60 pA and a charging voltage of 4 V. The estimated contact resistance is between 10 7 and 10 12 . Finally, this inspection method is applied to wafers manufactured for a static random access memory device. Accordingly, the gray scales of defective plugs formed for shared contact patterns are classified into two levels. The resistances of these defects are estimated from the calibration curve. The estimated resistances of the lower contrast defects (with an accuracy of about one order of magnitude) agree well with the resistances measured using a nanoprober. The resistances of the higher contrast defects are estimated as well, although they are too high to be measured using a nanoprober. C 2010 Society of Photo-Optical Instrumentation Engineers.

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Advanced inspection technique for deep-submicron and high-aspect-ratio contact holes

Cited by 8 publications

References 7 publications

Dielectric-thickness dependence of damage induced by electron-beam irradiation of MNOS gate pattern

Dielectric-thickness dependence of damage induced by electron-beam irradiation of MNOS gate pattern

Robust and efficient image processing scheme for electron beam LSI wafer pattern inspection

Quantitative measurement of voltage contrast in scanning electron microscope images for in-line resistance inspection of wafers

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