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Ultra-low switching power (∼1/50th–1/2250th that of a Ge2Sb2Te5 device) was obtained in a SnXTe100−X/Sb2Te3 diluted superlattice (SL) device (X = 10, 20, and 35 at. %). XRD analysis showed that there was little coexistence of the SnTe/Sb2Te3 SL, Bi2Te3-type SnSbTe-alloy and Te phases. Detailed crystallographic analysis showed that there is a high probability that the SnSbTe-alloy phase independently changed into a SL structure. This self-assembled SL structure had a vacancy layer in a specific Te layer. Some phenomenon, such as Sn switching, in the self-assembled SL might lead to the ultra-low switching power.

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Power efficient SoC design for embedded applications requires several independent power-domains where the power of unused blocks can be turned off. An SoC for mobile phones [1] defines 23 hierarchical power domains but most of the power domains are assigned for peripheral IPs that mainly use low-leakage high-V t transistors. Since high-performance multiprocessor SoCs use leaky low-V t transistors for CPU sections, leakage power savings of these CPU sections is a primary objective. We develop an SoC with 8 processor cores and 8 user RAMs (1 per core) targeted for power-efficient high-performance embedded applications. We assign these 16 blocks to separate power domains so that they can be independently be powered off. A resume mode is also introduced where the power of the CPU is off and the user RAM is on for fast resume operation. An automatic parallelizing compiler schedules tasks for each CPU core and also performs power management for each CPU core [2]. With the help of this compiler, each processor core can operate at a different frequency or even dynamically stop the clock to maintain processing performance while reducing average operating power consumption [3]. The compiler also executes power-off control of unnecessary CPU cores.The three design highlights of our SoC are as follows. First, the 8-processor core SoC is capable of executing 8640 MIPS at 600MHz for Dhrystone 2.1. It consumes 2.8W at 1.0V including leakage. Four CPU cores are combined to form a cluster, and a snoop controller maintains cache coherency inside the cluster. Second, the 8 processor cores and 8 user RAMs are assigned to separate power domains so that the power supply of unused CPUs can be cut off to reduce the leakage power. Each CPU has 5 power modes and an automatic parallelizing compiler optimizes total power consumption by controlling each CPU's power mode. Third, the 8-processor core SoC provides barrier registers for CPU synchronization. Software uses these registers for fast synchronization between CPUs. The compiler uses this synchronization mechanism effectively for scheduling the tasks. Figure 4.5.1 shows chip features. Figure 4.5.2 shows the block diagram of our SoC. Our SoC consists of two clusters where each cluster has 4 CPU cores. Each processor-core contains a CPU, an FPU, 16KB I/D caches, 8KB and 32KB I/D local RAM and 64KB user RAM (URAM). Within the cluster, there is a snoop controller (SNC) that maintains data cache coherency among processor cores. The SNC also broadcasts instruction-cache block invalidation (ICBI) instructions to other CPU instruction caches. Memory controllers such as DDR2-SDRAM and SRAM, and DMA controllers are connected through on-chip system bus (SHwy), which is a packet-based split transaction bus system.The power-domain view is shown in Figure 4.5.3. Each CPU is allocated to a separate power domain so that the power supply can be cut off when unused. Two power domains (Cn and Un, for n ranging from 0 to 7) are assigned to each CPU, where Un is allocated only for URAM. By keeping power of ...