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the local memories and the shared memory (i.e. the CSM A heterogeneous multiprocessor on a chip has been or the local memories on other PE). The DTU provides designed and implemented. It consists of 2 CPUs and the features of scatter/gather commands and command 2 DRPs (Dynamic Reconfigurable Processors). The chains as well. Since the DTU works in parallel with the design of DRP was intended to achieve PE core, processing and data transfer can be overlapped, high-performance in a small area to be integrated on a and pipelined parallel processing is enabled. SoC for embedded systems. Memory architecture of Lastly, the power control register (FVR) is attached to CPUs and DRPs were unified to improve program-each PE and is used to control the frequency and voltage ming and compiling efficiency. 54x AAC-LC stereo of the PE for power reduction. encoding has been enabled with 2 DRPs at 300MHz and 2 CPUs at 600MHz. Flexible Engine/Generic ALU array Keywords: multiprocessor, dynamic reconfigurable proc-Flexible Engine/Generic ALU array (FE-GA) is a coarse essor, SoC, embedded system and AAC grain dynamic reconfigurable processor (DRP) [4]. We have defined the architecture to be suitable for embedded

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