Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding

Shikano, Hiroaki; Ito, Masaki; Onouchi, Masafumi; Todaka, Takashi; Tsunoda, Teruo; Kodama, Tetsuya; Uchiyama, Kunio; Odaka, Takahiro; Kamei, Takeshi; Nagahama, E.; Kusaoke, M.; Nitta, Yusuke; Wada, Yasutaka; Kimura, Keiji; Kasahara, Hironori

doi:10.1109/jssc.2008.917531

Cited by 17 publications

(24 citation statements)

References 10 publications

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“…These methods are proposed with an assumption that random access is possible and the allocated data can be accessed at any time from any memory address. In recent heterogeneous multicore processors [1], address generation units (AGUs) are included in the accelerator cores to increase the address generation speed. AGUs contain simple hardware units such as adders and counters to reduce the accelerator core area.…”

Section: Previous Partitioning Methods and Their Problems Inmentioning

confidence: 99%

“…In this example, the pixel [0,1] is copied to two memory locations: 0x01 and 0x05. Similarly, the pixel [1,2] is copied to 0x04 and 0x08. Even though we need to access only 8 pixels, we have to transfer 10 pixels to the local memory modules where two of them are duplicated.…”

Section: Previous Partitioning Methods and Their Problems Inmentioning

confidence: 99%

“…In this paper, we discuss how to implement block matching on heterogeneous processors with reconfigurable accelerators. We use the heterogeneous multicore processor called "RP1" proposed in [1]. The block diagram of RP1 processor is shon in Fig.…”

Section: Processor Architecturementioning

confidence: 99%

“…Figure 16 shows the processor board used for the evaluation. It has the RP1 heterogeneous multi-core processor [1] that contains 4 CPU cores and 2 FE-GA cores. Figure 17 shows the flow-chart of the scheduling and the allocation of the SAD computation process.…”

Section: Context Partitioning Of the Block Matching Algorithmmentioning

confidence: 99%

“…Therefore, an effective way to implement image processing in mobile appliances is to use low-power heterogeneous multicore processors that contain different cores such as CPUs and accelerators. Examples of heterogeneous multi-core processors are [1] and [2]. The former has multiple cores of CPUs and dynamically reconfigurable ALU arrays.…”

Section: Introductionmentioning

confidence: 99%

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Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors

Waidyasooriya

Ohbayashi

Hariyama

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYAccelerator cores in low-power heterogeneous processors have on-chip local memories to enable parallel data access. The memory capacities of the local memories are very small. Therefore, the data should be transferred from the global memory to the local memories many times. These data transfers greatly increase the total processing time. Memory allocation technique to increase the data sharing is a good solution to this problem. However, when using reconfigurable cores, the data must be shared among multiple contexts. However, conventional context partitioning methods only consider how to reuse limited hardware resources in different time slots. They do not consider the data sharing. This paper proposes a context partitioning method to share both the hardware resources and the local memory data. According to the experimental results, the proposed method reduces the processing time by more than 87% compared to conventional context partitioning techniques.

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Section: Previous Partitioning Methods and Their Problems Inmentioning

confidence: 99%

Section: Previous Partitioning Methods and Their Problems Inmentioning

confidence: 99%

Section: Processor Architecturementioning

confidence: 99%

Section: Context Partitioning Of the Block Matching Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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