ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference 2013
DOI: 10.1109/asmc.2013.6552760
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Advanced litho-cluster control via integrated in-chip metrology

Abstract: The high-end semiconductor lithography requirements for overlay and focus control in near-future ITRS nodes are at subnanometer level. This development is extremely challenging for the metrology precision and accuracy, as scaling down to the subangstrom level is required for this. On top of the extreme metrology requirements, direct feed-back control of the lithographic steps is needed to meet the future node requirements. Integrated metrology with in-chip measurements, advanced sampling and control-mechanism … Show more

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Cited by 4 publications
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“…Unfortunately this assumption is unrealistic and leads to inaccuracy [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. There are different types of metrology target asymmetries that contaminate the signal and mix with the overlay-induced asymmetry.…”
Section: Overlay Metrology In the Accuracy Agementioning
confidence: 99%
“…Unfortunately this assumption is unrealistic and leads to inaccuracy [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. There are different types of metrology target asymmetries that contaminate the signal and mix with the overlay-induced asymmetry.…”
Section: Overlay Metrology In the Accuracy Agementioning
confidence: 99%