Improving on-product performance at litho using integrated diffraction-based metrology and computationally designed device-like targets fit for advanced technologies (incl. FinFET)

Chen, Kai-Hsiung; Huang, Guo-Tsai; Ks, Chen; Hsieh, Chih‐Wei; Yc, Chen; Ke, Chih-Ming; Gau, Tsai‐Sheng; Ku, Y. C.; Bhattacharyya, Kaustuve; Huang, Jacky; Boef, Arie den; Schaar, Maurits van der; Maassen, Martijn; Plug, Reinder; Zhang, Youping; Meyer, S.; Veen, Martijn van; Ruiter, Chris de; Wu, Jon; Xu, Hua; Chow, T.W.S.; Chen, Charlie; Verhoeven, Eric; Li, Pu; Hinnen, Paul; Storms, Greet; Pao, Kelvin; Zhang, Gary; Fouquet, Christophe; Mori, Takuya

doi:10.1117/12.2047098

Cited by 10 publications

(3 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This computational approach can be extended to the selection of the best possible measurement setting where the sensitivity to asymmetric grating distortion is minimized. These approaches already take us close to the regime of sub-nm accuracy [37] as shown in figure 17.…”

Section: Overlay Metrologymentioning

confidence: 77%

Optical wafer metrology sensors for process-robust CD and overlay control in semiconductor device manufacturing

Boef

2016

Surf. Topogr.: Metrol. Prop.

View full text Add to dashboard Cite

This paper presents three optical wafer metrology sensors that are used in lithography for robustly measuring the shape and position of wafers and device patterns on these wafers. The first two sensors are a level sensor and an alignment sensor that measure, respectively, a wafer height map and a wafer position before a new pattern is printed on the wafer. The third sensor is an optical scatterometer that measures critical dimension-variations and overlay after the resist has been exposed and developed. These sensors have different optical concepts but they share the same challenge that sub-nm precision is required at high throughput on a large variety of processed wafers and in the presence of unknown wafer processing variations. It is the purpose of this paper to explain these challenges in more detail and give an overview of the various solutions that have been introduced over the years to come to process-robust optical wafer metrology.

show abstract

Section: Overlay Metrologymentioning

confidence: 77%

Optical wafer metrology sensors for process-robust CD and overlay control in semiconductor device manufacturing

Boef

2016

Surf. Topogr.: Metrol. Prop.

View full text Add to dashboard Cite

show abstract

“…In order to address the above challenge a multi wavelength approach is taken. This is synonymous to an "YieldStar Self-Reference" (YSSR) creation and was discussed in previous publications 2,4 . Overlay calculated with multi wavelength (instead of a single wavelength) using this method 2 (shown below) inherently corrects for the asymmetry error in overlay.…”

Section: Grating Imbalance Grating Asymmetrymentioning

confidence: 96%

“…We therefore need to have an algorithm that will filter out these asymmetry (nonlinear pixels). This requires the measurement to see the full target radiometric image (available via image plane detection 4 with a large metrology spot) in order to avoid areas on the grating that are adversely impacted by processing effect. Combining Leveling and Alignment results in a dense overlay grid that can be used for better OV control.…”

Section: Grating Imbalance Grating Asymmetrymentioning

confidence: 99%

Tough road ahead for device overlay and edge placement error

Bhattacharyya

2019

Metrology, Inspection, and Process Control for Microlithography XXXIII

Self Cite

View full text Add to dashboard Cite

During the last several years we have seen an impressive drive in the industry to continue to innovate in order to keep up with the challenging requirements of overlay in multi-patterning processes. A major part of these efforts is spent in opening up of the flexibility in control knobs on process tools (mostly lithography and etch) enabling the high order actuation capability. In order to feed this high order actuation, it has also become important to address the need of input data accuracy, driving up the demand for improved metrology accuracy and sampling. Adding to the complexity, it has also become important to address edge placement error (EPE). EPE is basically the pattern fidelity of a device structure created by a multi-patterning process, defined as the relative displacement of the edges of two features from their intended target position. Here local CD error is an important parameter in addition to overlay. EPE requirements of a "single digit nanometer number" is now a harsh reality in 5nm nodes and below. In this technical presentation we will review the above developments and remaining gaps in technology (litho and dimensional metrology applications), as well as design and integration. Mitigation of such challenges need a large team effort that is industry-wide and not just limited to litho.

show abstract

On-product performance improvement via advanced litho-cluster control using integrated metrology and multi-layer overlay target

Bhattacharyya¹,

Maassen²,

Schmitt-Weaver³

et al. 2015

2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

View full text Add to dashboard Cite

Improving on-product performance at litho using integrated diffraction-based metrology and computationally designed device-like targets fit for advanced technologies (incl. FinFET)

Cited by 10 publications

References 4 publications

Optical wafer metrology sensors for process-robust CD and overlay control in semiconductor device manufacturing

Optical wafer metrology sensors for process-robust CD and overlay control in semiconductor device manufacturing

Tough road ahead for device overlay and edge placement error

On-product performance improvement via advanced litho-cluster control using integrated metrology and multi-layer overlay target

Contact Info

Product

Resources

About