Tough road ahead for device overlay and edge placement error

Abstract

During the last several years we have seen an impressive drive in the industry to continue to innovate in order to keep up with the challenging requirements of overlay in multi-patterning processes. A major part of these efforts is spent in opening up of the flexibility in control knobs on process tools (mostly lithography and etch) enabling the high order actuation capability. In order to feed this high order actuation, it has also become important to address the need of input data accuracy, driving up the demand for improved metrology accuracy and sampling. Adding to the complexity, it has also become important to address edge placement error (EPE). EPE is basically the pattern fidelity of a device structure created by a multi-patterning process, defined as the relative displacement of the edges of two features from their intended target position. Here local CD error is an important parameter in addition to overlay. EPE requirements of a "single digit nanometer number" is now a harsh reality in 5nm nodes and below. In this technical presentation we will review the above developments and remaining gaps in technology (litho and dimensional metrology applications), as well as design and integration. Mitigation of such challenges need a large team effort that is industry-wide and not just limited to litho.

Extreme ultraviolet lithography reticle local CD uniformity correlation to wafer local CD uniformity

“…The stochastic CD error at the mask is a significant contributor to the local CD error component of the Edge Placement Error (EPE) budget, as illustrated in Figure 1(a) [1]. Furthermore it is expected that as nodes advance the relative contribution from local CD errors / stochastics will increase, reaching approximately 50% of the EPE budget by the 3nm node, as illustrated in Figure 1(b) [2]. Figure 1.…”

“…Figure 1. (a) Edge Placement Error budget contributors [1] (b) Change in EPE budget contributors as a function of logic node [2] In addition to the EPE budget contribution, stochastic CD error on the mask affects the minimum allowable wafer exposure dose to meet wafer LCDU targets. Figure 2 below [3] illustrates how the dose to hit various wafer LCDU targets is a function of the mask LCDU, and how this function depends on the type of mask and type of resist used.…”

Analysis of Line-Edge Roughness Using EUV Scatterometry

“…These lamellar gratings are affected by line-edge roughness that has been identified as the ultimate limiting factor in the production of nanostructured surfaces in the semiconductor industry [1]. State-of-the-art integrated electronic circuits are produced in several steps and any misplacement of the edge position can lead to a complete failure of the features [2]. Therefore, at present, almost 50% of the processes in production consist of metrology [3].…”

“…Overlay metrology is used to characterize displacements between patterned layers with optical wavelengths. However, the accuracy is limited when asymmetry is present on the studied targets [2]. Grazing-incidence small-angle X-ray scattering (GISAXS) has been proposed as an alternative method for characterizing nanostructured surfaces.…”

New registration calibration strategies for MBMW tools by PROVE measurements

“…Within the EPE budget the contribution due to resist and photon stochastics becomes larger with advanced nodes and is the hardest or is even impossible to come by. Therefore, we must improve the overlay error contribution to create room for stochastics [2].…”