2015 IEEE 65th Electronic Components and Technology Conference (ECTC) 2015
DOI: 10.1109/ectc.2015.7159695
|View full text |Cite
|
Sign up to set email alerts
|

Advanced multi-sites testing methodology after wafer singulation for WLPs process

Abstract: With the strong grow of smartphone, wearable devices and the upcoming IoT in our life. Wafer level packages offer the lowest total cost of higher semiconductor content with leveraging the smallest die size and the highest performing, most reliable on the market today. The existing testing process of WLPs encounter the new challenges from thinner and warpage wafers which will impact high parallelism multi-sites testing performance and KGDs of wafer singulation.Following the same process as "chip probing (CP)", … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Year Published

2021
2021
2023
2023

Publication Types

Select...
2

Relationship

0
2

Authors

Journals

citations
Cited by 2 publications
references
References 6 publications
0
0
0
Order By: Relevance