With the strong grow of smartphone, wearable devices and the upcoming IoT in our life. Wafer level packages offer the lowest total cost of higher semiconductor content with leveraging the smallest die size and the highest performing, most reliable on the market today. The existing testing process of WLPs encounter the new challenges from thinner and warpage wafers which will impact high parallelism multi-sites testing performance and KGDs of wafer singulation.Following the same process as "chip probing (CP)", the function testing of WLP is designed at "before singulation". There is the final testing (FT) after CP for packaging process, but no for WLPs. The best solution shall be to do the functional testing after wafer singulation, as same as FT of packaging process. The existing solution is to do testing for singulated dies on film-frame, but it still faces the problem on the multi-sites testing. The die position gets changed after wafer singulation, so the testing site numbers must be reduced and cannot be same as CP is.The new solution will be presented in this paper. The wafer is mounted on the glass carrier with double-sided adhesive tape. The glass and tape size are designed as same as wafer form, so it can be handled as a normal wafer. The dies are firmly stuck on the glass with double-sided adhesive tape during wafer singulation. The position of the dies is no displacement, so the multi-sites testing can be implemented and the testing tool shall be same as the one of CP. The tape adhesion is a kind of thermo-release type, so there is no needle ejector of the die-sort machine. Because of no mechanical contact, it can handle thinner dies safely.Based on the new process, the singular dies are handled by wafer form. It is easy to be integrated with existing process of wafer singulation, testing and die-sorting. A minimum process change gains a maximum multi-sites testing performance. In summary, the wafer mounted on glass with double-sided adhesive tape is the best solution on multi-sites testing methodology after wafer singulation.978-1-4799-8609-5/15/$31.00 ©2015 IEEE