Advanced self-organizing maps using binary weight vector and its digital hardware design

Yamakawa, Takeshi; Horio, Keiichi; Hiratsuka, Tomokazu

doi:10.1109/iconip.2002.1202837

Cited by 7 publications

(14 citation statements)

References 10 publications

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“…INTRODUCTION T HE original Self Organizing Map (SOM) proposed by Kohonen [1] consists of two layers; the input and the competitive layers. It is an unsupervised neural network with competitive learning models that captures the topology and probability distribution of input data, which facilitates clustering and classification in pattern recognition [2] , [3], [4].…”

Section: A Binary Self-organizing Map and Its Fpga Implementation Kofmentioning

confidence: 99%

“…al. in [3] proposed a binary weighted vector SOM and simulated it in hardware. The proposed SOM uses binary data for both input and weight vectors.…”

Section: A Binary Self-organizing Map and Its Fpga Implementation Kofmentioning

confidence: 99%

“…The design of the binary weighted SOM is five times faster than the real number weighted SOM in software and 140 times faster in hardware [3]. This highlights a key principle -that the most successful design will take account of the nature of the hardware architecture.…”

Section: A Binary Self-organizing Map and Its Fpga Implementation Kofmentioning

confidence: 99%

“…The bSOM trammg algorithm is discussed below, and compared and contrasted with the original SOM algorithm and Yamakawa's [3] implementation. shows that increasing the number of training iterations makes no significant difference to the final results, confirming that the bSOM requires fewer iterations to converge, as compared to the original SOM and that presented in [3].…”

Section: Input Layer Ne Urons Imentioning

confidence: 99%

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A binary Self-Organizing Map and its FPGA implementation

Appiah

Hunter

Meng

et al. 2009

2009 International Joint Conference on Neural Networks

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The vector components of the winning node Wk with minimum distance Di; is then updated as follows where TJ is the learning rate. The topological ordering property is imposed by also updating weight vectors of nodes in the neighbourhood of the winning node. This can be achieved by the following learning rulewhere N j is a neighbourhood function (defining the region around Wk ) based on the topological displacement of neighbouring neuron from the winning neuron. The size of N j decreases as training progresses.In the vast majority of implementations, the SOM input data and neurons are represented by real numbers, making it difficult to implement on a hardware architecture like the Field Programmable Gate Array (FPGA). However, in many applications the data is either presented as a binary string, or may be conveniently recoded as such (a "binary signature"). For example, in image processing applications a bank of Haar filters produces a long binary signature. In this paper we present a new learning algorithm which takes binary inputs and maintains tri-state weights (neuron) in the SOM. We also present the FPGA implementation of this binary Self Organizing Map (bSOM). The bSOM is designed for efficient hardware implementation, having both greatly reduced circuit size compared to a real-valued SOM, and exceptionally fast execution and training times.In section II, we review previous implementations of SOM on hardware architectures. The novel bSOM algorithm is then presented in III, followed by its FPGA implementation in section IV. Section V, presents the experimental results in software and hardware, and we conclude in section VI.During training, the "nearest" neuron prototype vector to the input vector is identified -this is called the "winning" neuron -using a distance metric, D. The Euclidean distance is most frequently used as the metric.For a given network with M neurons and N-dimensional input vector x, the distance for neuron with weight vector Wj (j < M) is given by

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Section: A Binary Self-organizing Map and Its Fpga Implementation Kofmentioning

confidence: 99%

“…al. in [3] proposed a binary weighted vector SOM and simulated it in hardware. The proposed SOM uses binary data for both input and weight vectors.…”

Section: A Binary Self-organizing Map and Its Fpga Implementation Kofmentioning

confidence: 99%

Section: A Binary Self-organizing Map and Its Fpga Implementation Kofmentioning

confidence: 99%

Section: Input Layer Ne Urons Imentioning

confidence: 99%

See 2 more Smart Citations

A binary Self-Organizing Map and its FPGA implementation

Appiah

Hunter

Meng

et al. 2009

2009 International Joint Conference on Neural Networks

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“…For instance, [6] addresses the challenging issue of predicting the remaining useful life for ball bearing prognostics. On the other hand, few additional works [2,12,17] have proposed different hardware architectures for the implementation of self-organizing maps, but all targeting other applications than the system maintenance.…”

Section: Introductionmentioning

confidence: 99%

Design of an embedded system for the proactive maintenance of electrical valves

Gonçalves

Bosa

Henriques

et al. 2009

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

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This paper presents a proactive maintenance scheme for the detection and diagnosis of faults in electrical valves. In our case study, these actuators are used for controlling the flow in an oil distribution network. An embedded system implements selforganizing maps for the detection and classification of faults that lead to deviations either on torque, or on the valve opening position. For fault detection, the map is trained using a mathematical model devised for the electrical valve. For fault classification, training is performed by fault injection based on parameter deviations over this same mathematical model. In both cases, the maps store the energies of the torque and the opening position that are computed using the wavelet packet transform. Once the maps are trained, the embedded system is ready for online monitoring the actuator. During the on-line testing phase, the embedded system computes the best matching between an acquired input vector (current torque and position energies) and the synaptic weight vector of the trained map. This matching is quantified by computing the Euclidean distance between these vectors and guide the fault detection and classification steps. The complete scheme was prototyped using FPGAs. The results obtained for area, performance and memory requirements point out to a low cost, promising solution for embedding maintenance in electrical actuators.

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