Advanced system on a chip design based on controllable-polarity FETs

Reconfigurable silicon nanowire field-effect transistors (RFETs) combine the functionality of classical unipolar p-type and n-type FETs in one universal device. In this paper, we show devices exhibiting full symmetry between p-and n-functionality, while having identical geometry. Scaling trends and feasibility for digital circuit integration are evaluated based on TCAD simulations. The method of logical effort is applied to analyze fundamental differences in circuit topology using this unique type of multigate transistors. We introduce a set of multifunctional logic gates based on RFETs providing all basic Boolean functions, including NAND/NOR, AND/OR, and XOR/XNOR, and compared them with classical implementations. Two 1-bit full adders based on those gates are presented as an insightful example that RFETs are one possible solution to increase the system functionality. Moreover, it is shown that an asymmetric transistor layout with individual optimization of both top gates can be used to increase the speed of those circuits.

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“…Also new solutions to build sequential circuits as proposed by Gaillardon et al [19], [26] have to be found.…”

Section: -Bit Full Adder Design Examplesmentioning

confidence: 99%

Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

Trommer

Heinzig

Baldauf

et al. 2015

IEEE Trans. Nanotechnology

103

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“…Dense regular arrays of such cells can be fabricated, which are consecutively hard programmed by the metallization to the desired gate functionality. Doing so, it is possible to design logic circuits in a more compact memory array-like style, increasing the layout regularity [38,62]. From those patterns a transmission gate 1-bit full adder with only 14 transistors including input inverters can be built.…”

Section: Logic Circuits With Reconfigurable Field Effect Transistorsmentioning

confidence: 99%

“…Employing MIGFETs also a fully static 1-bit adder implementation amounting to a total of 18 transistors is possible [9,54]. Also first designs of more complex combinational and sequential logic, such as true single phase clocking (TSPC) flip-flops, parallel counters and compressors have been proposed using MIGFETs [62,63]. Finally, the unique properties of RFETs, such as equivalence of pull-up and pull-down networks have led to some interesting applications in hardware security and resilience [64,65].…”

Section: Logic Circuits With Reconfigurable Field Effect Transistorsmentioning

confidence: 99%

The RFET—a reconfigurable nanowire transistor and its application to novel electronic circuits and systems

Mikolajick

Heinzig

Trommer

et al. 2017

Semicond. Sci. Technol.

113

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With CMOS scaling reaching physical limits in the next decade, new approaches are required to enhance the functionality of electronic systems. Reconfigurability on the device level promises to realize more complex systems with a lower device count. In the last five years a number of interesting concepts have been proposed to realize such a device level reconfiguration. Among these the reconfigurable field effect transistor (RFET), a device that can be configured between an n-channel and p-channel behavior by applying an electrical signal, can be considered as an end-of-roadmap extension of current technology with only small modifications and even simplifications to the process flow. This article gives a review on the RFET basics and current status. In the first sections state-of-the-art of reconfigurable devices will be summarized and the RFET will be introduced together with related devices based on silicon nanowire technology. The device optimization with respect to device symmetry and performance will be discussed next. The potential of the RFET device technology will then be shown by discussing selected circuit implementations making use of the unique advantages of this device concept. The basic device concept was also extended towards applications in flexible devices and sensors, also extending the capabilities towards so-called More-than-Moore applications where new functionalities are implemented in CMOS-based processes. Finally, the prospects of RFET device technology will be discussed.

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“…RFET (figure 1(a)) can be configured as nMOS or pMOS device by applying an appropriate bias. This feature has been demonstrated to realize logic circuits with a lesser number of transistors compared to existing technology [4][5][6][7][8]. In literature, RFET has been demonstrated to implement logic gates with a lower transistor count i.e.…”

Section: Introductionmentioning

confidence: 99%

A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

Nirala¹,

Semwal²,

Kranti³

2022

Semicond. Sci. Technol.

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Capacitorless dynamic memory (1T-DRAM) operation in a reconfigurable transistor (RFET) is critically governed by different lengths associated with the architecture. These lengths consisting of ungated region (LUG), control gate (LCG), polarity gate (LPG), storage region length (LS), and total length (LT) can be sensitive to the fabrication process, and hence, critical for 1T-DRAM. This work presents an insightful critique of the above mentioned lengths for realising optimal 1T-DRAM performance. It is shown that RFET with highest values of LS/LT and LCG/LT shows good short channel immunity but does not necessarily ensure enhanced 1T-DRAM metrics. Results indicate that for a fixed LT, retention time (RT) can vary over a wide range (550 ms to 8.7 s) depending on the values of LS/LT and LCG/LT, and hence, appropriate optimization is imperative. The work contributes towards better understanding and optimizing LCG/LT to ensure improved 1T-DRAM metrics in terms of enhanced retention (> 64 ms), acceptable sense margin (> 6 µA/µm), current ratio (> 104) with low values of read (2 ns) and write (1 ns) time to further extend multi-functional facets of nanoscale RFETs for memory applications. In addition, the effect of traps, process sensitivity, reduced number of voltage levels, and disturbance caused by shared word line/bit line are also analysed in this work. Results indicate that state ‘0’ of the cell sharing bit line (BL) with the selected cell is strongly affected by BL disturbance. Word line (WL) disturbance primarily impacts state ‘1’ of the cell sharing WL with selected cell (only for write 1 and read operations).

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Advanced system on a chip design based on controllable-polarity FETs

Cited by 15 publications

References 13 publications

Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

The RFET—a reconfigurable nanowire transistor and its application to novel electronic circuits and systems

A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

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