“…The number of rows (n r (i) ) is considered as variable for a given circuit in order to represent the circuit optimally. For example, the 1408 gates of the apex1 benchmark is mapped on the array of 19x189 nodes; however only 1,5,7,14,17,26,43,57,84,117,142,177,189,187,139,89,51,27,40 gates are utilized in columns i ¼ 1. . .19.…”