Advanced Techniques in Logic Synthesis, Optimizations and Applications

Кравец, В. В.; Mishchenko, A. T.; Krishnasamy, Smita; Modi, Nilesh; Brayton, Robert K.; Puri, Ruchir; Gulati, Kanupriya; Khatri, Sunil P.

doi:10.1007/978-1-4419-7518-8

Cited by 5 publications

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On a Polytime Factorization Algorithm for Multilinear Polynomials over $$\mathbb {F}_2$$

Emelyanov

Ponomaryov

2018

Developments in Language Theory

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In 2010, A. Shpilka and I. Volkovich established a prominent result on the equivalence of polynomial factorization and identity testing. It follows from their result that a multilinear polynomial over the finite field of order 2 can be factored in time cubic in the size of the polynomial given as a string. Later, we have rediscovered this result and provided a simple factorization algorithm based on computations over derivatives of multilinear polynomials. The algorithm has been applied to solve problems of compact representation of various combinatorial structures, including Boolean functions and relational data tables. In this paper, we describe an improvement of this factorization algorithm and report on preliminary experimental analysis.

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On a Polytime Factorization Algorithm for Multilinear Polynomials over $$\mathbb {F}_2$$

Emelyanov

Ponomaryov

2018

Developments in Language Theory

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Extending Boolean Methods for Scalable Logic Synthesis

et al. 2020

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Improving Characteristics of FSMs With Mixed Codes of Outputs

et al. 2022

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Practically, any digital system includes sequential blocks. This paper considers a case when LUT-based sequential blocks are represented by Mealy finite state machines (FSMs). The LUT count is one of the most important characteristics of an FSM circuit. In this paper, a method is proposed which aims at decreasing the LUT counts of FPGA-based Mealy FSMs with mixed encoding of the collections of outputs. To do it, a method of encoding of the fields of compatible states is proposed. The proposed approach leads to LUT-based Mealy FSM circuits having three levels of logic blocks. Each function for any logic level is represented by a circuit including a single LUT. There is given an example of FSM synthesis with the proposed method. The experiments are conducted using standard benchmark FSMs. The results of experiments show that the proposed approach produces LUT-based circuits with fewer LUTs than it is for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, the mixed encoding the collections of outputs). The LUT count is decreased by an average of 6.97 to 62.85 percent. These improvements are accompanied by a slight decrease in the maximum operating frequency. The frequency is decreased by up to 8.09%. The advantages of the proposed method increase as the number of FSM inputs and states increases. INDEX TERMSMealy FSM, FPGA, LUT, synthesis, mixed encoding of collections of outputs, fields of compatible states.

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Advanced Techniques in Logic Synthesis, Optimizations and Applications

Cited by 5 publications

References 0 publications

On a Polytime Factorization Algorithm for Multilinear Polynomials over $$\mathbb {F}_2$$

On a Polytime Factorization Algorithm for Multilinear Polynomials over $$\mathbb {F}_2$$

Extending Boolean Methods for Scalable Logic Synthesis

Improving Characteristics of FSMs With Mixed Codes of Outputs

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