Advanced test methodology for complex SoCs

Jagannadha, Pavan Kumar Datla; Yilmaz, Mahmut; Sonawane, Milind; Chadalavada, Sailendra; Sarangi, Shantanu; Bhaskaran, Bonita; Abdollahian, Ayub

doi:10.1109/test.2016.7805857

Cited by 7 publications

(2 citation statements)

References 21 publications

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“…So, the time taken to apply test vectors turned into an increasing worry. Currently, the very large-scale integration (VLSI) industry is experiencing a huge difficulty in testing complex SoC designs [3]. Scan design [4] is the DFT method that can test an extremely complex design with good fault detection.…”

Section: Introductionmentioning

confidence: 99%

An effective way to generate the shift timing constraints and sanity checks

Afridi¹,

Shylashree²,

Tunga

et al. 2023

IJEECS

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Design for testability (DFT) is a technique, which facilitates a design to become testable after fabrication. As the technology node is shrinking, complexity of the system-on-chip (SoC) becomes high and inserting DFT and verifying its timing becomes complex. For these complex SoC, generating DFT timing constraints becomes difficult in shift mode and the time required for the generation of these timing constraints is also more. A new methodology proposed to overcome these issues. The main objective of this work is to propose the flow for generating DFT timing constraints for the complex SoC in shift mode, by dividing the design blocks into scan blocks and non-scan blocks. To target the whole design without getting all paths reported, relaxation of the setup, and hold time for non-scan blocks plays crucial role. If not, the time taken to generate DFT timing constraints would be more. Implemented methodology of this paper includes design setup, timing exceptions, and synopsys design constraints (SDC) generation for DFT timing. Design setup consists of all pre-requisites for design such as netlists, timing libraries, and exceptions. Synopsys primetime (PT Shell) is used for all the timing-related checks. Compared to conventional methods, the proposed flow reduces the overall time by 40% to generate constraints.

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Section: Introductionmentioning

confidence: 99%

An effective way to generate the shift timing constraints and sanity checks

Afridi¹,

Shylashree²,

Tunga

et al. 2023

IJEECS

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“…1) Overheating due to the accumulative impact of shift power may damage a circuit or increase test cost. 2) Shift failure due to excessive shift power induced IR-drop along clock paths or in the power supply of scan flip-flops will cause wrong data to be shifted [6]- [8]. 3) Capture failure due to excessive capture power induced IR-drop along data paths will cause a false response to be captured.…”

Section: Introductionmentioning

confidence: 99%

GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting

SHI,

HOLST,

WEN

2023

IEICE Trans. Inf. & Syst.

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High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems:(1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC'99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.

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