Advanced tungsten plug process for beyond nanometer technology

Luoh, Tuung; Su, Chin-Ta; Yang, Tahone; Chen, Kuang-Chao; Lu, Chih‐Yuan

doi:10.1016/j.mee.2008.04.030

Cited by 31 publications

(12 citation statements)

References 14 publications

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“…As the filling metal, the atomic layer deposition Tungsten (ALD W) is widely applied due to better step coverage and conformity of deposited thin films. Usually, there are two kinds of ALD W process, one is using Diborane (B 2 H 6 ) precursor, and the other is using silane (SiH 4 ) [ 293 , 294 ]. The FinFET devices with different ALD W precursors show obvious sensitivity of electrical and reliability characteristics.…”

Section: Advanced Devices Reliablitymentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Section: Advanced Devices Reliablitymentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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“…The common precursors used for ALD W are SiH 4 [95,96,97,98,99,100,101,102,103,104,105,106,107,108], Si 2 H 6 [99], and B 2 H 6 [100,101,102,103]. Different precursors will form films with different phases.…”

Section: Interconnections In Cmosmentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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“…The ALD-W films deposited by using diborane, B 2 H 6 , as a reducing agent of WF 6 was reported in 2002 by Yang et al [82] and further studied by Kim et al [83,84]. The ALD-W process using silane, SiH 4 , was also extensively investigated, based on the similar reaction mechanism consideration [85,86]. All the above works were mainly targeting the application as the seed layer of CVD for W contact plug.…”

Section: Ald Of P-type Metal Gatementioning

confidence: 99%

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

Zhao

Xiang

2019

Applied Sciences

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The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

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Advanced tungsten plug process for beyond nanometer technology

Cited by 31 publications

References 14 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

Miniaturization of CMOS

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

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