Advanced wireless digital baseband signal processing beyond 100 Gbit/s

Abstract

The continuing trend towards higher data rates in wireless communication systems will, in addition to a higher spectral efficiency and lowest signal processing latencies, lead to throughput requirements for the digital baseband signal processing beyond 100 Gbit/s, which is at least one order of magnitude higher than the tens of Gbit/s targeted in the 5G standardization. At the same time, advances in silicon technology due to shrinking feature sizes and increased performance parameters alone won't provide the necessary gain, especially in energy efficiency for wireless transceivers, which have tightly constrained power and energy budgets. In this paper, we highlight the challenges for wireless digital baseband signal processing beyond 100 Gbit/s and the limitations of today's architectures. Our focus lies on the channel decoding and MIMO detection, which are major sources of complexity in digital baseband signal processing. We discuss techniques on algorithmic and architectural level, which aim to close this gap. For the first time we show Turbo-Code decoding techniques towards 100 Gbit/s and a complete MIMO receiver beyond 100 Gbit/s in 28 nm technology.

Fully Pipelined Iteration Unrolled Decoders the Road to TB/S Turbo Decoding

“…However, Turbo codes allow the utilization of functional level parallelism at the iteration level. Pipelining the half-iterations and connecting them to a single pipeline leads to a fourth architecture archetype: Fully Pipelined Iteration Unrolled (UXMAP): In this decoder architecture, complete frames are processed in parallel while traversing through the decoder pipeline [13], [26]. This allows for a very high throughput which is determined by the frame size and the achievable clock frequency, since one complete decoded frame is output per clock cycle, once the pipeline is completely filled.…”

Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology

“…Even if the implementation exploits all known techniques to improve LDPC-decoding efficiency, it still needs 12 mm 2 of silicon and consumes 5 W. Due to the consumed power and low flexibility due to fixed code rate, today's solutions have to be revised on an algorithmic level. Although it is possible to reduce the power of the FEC processor down to ∼600 mW by applying ultra-high scaled 7 nm technology [15]- [17], it is still far beyond the targeted limit of 1 W for the complete transceiver. This becomes even more challenging when code-rates lower than 13/16 and data rates > 100 Gbps are considered.…”

25 Years of Turbo Codes: From Mb/s to beyond 100 Gb/s

“…Early results of fully pipelined, iteration unrolled turbo decoding -a concept known from LDPC decoders [17], [18] suggest that throughputs beyond 100 Gb/s are possible [19]. To this end, a investigation of the error correcting performance of FPMAP decoders at high code rates and a detailed discussion of a iteration unrolled, fully pipelined turbo decoder is missing from literature.…”

“…Assuming a completely filled pipeline, this allows for the output of a complete decoded frame per clock cycle resulting in a very high throughput, which is only limited by the achievable clock frequency and frame size. The idea for this architecture was first presented in [19] but no detailed description, performance numbers or place & route results were given. To achieve throughput in the order of 100 Gb/s, decoder architectures with extreme parallelism like the FPMAP and UXMAP are needed.…”