Advances in Simultaneous Multithreading Testcase Generation Methods

Ludden, John M.; Rimon, Michal; Hickerson, Bryan; Adir, Allon

doi:10.1007/978-3-642-19583-9_15

Cited by 9 publications

(4 citation statements)

References 7 publications

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“…Consequently, there are relatively few of them. However, some randomness can still be added to self-checking test-cases using techniques such as random irritation by other threads [12], or by randomizing aspects of the scenario that do not change its essence (e.g., the type of load/store instructions used or the memory locations). Such randomness enables us to run the scenario many times in different flavors and timing situations and thus increase the coverage and the chances of finding bugs.…”

Section: Verifying Atomicitymentioning

confidence: 99%

Verification of Transactional Memory in POWER8

Adir¹,

Goodman²,

Hershcovich³

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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Transactional memory is a promising mechanism for synchronizing concurrent programs that eliminates locks at the expense of hardware complexity. Transactional memory is a hard feature to verify. First, transactions comprise several instructions that must be observed as a single global atomic operation. In addition, there are many reasons a transaction can fail. This results in a high level of non-determinism which must be tamed by the verification methodology. This paper describes the innovation that was applied to tools and methodology in pre-silicon simulation, acceleration and post-silicon in order to verify transactional memory in the IBM POWER8 processor core.

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Section: Verifying Atomicitymentioning

confidence: 99%

Verification of Transactional Memory in POWER8

Adir¹,

Goodman²,

Hershcovich³

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

Self Cite

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“…In publication [4] the concept of stress-functions (thread irritators) was introduced for simultaneous multithreading testing in IBM processors. Three methods of improving the test program generation were proposed: stress-function (thread), merged threads and replication of threads.…”

Section: Stress-functionsmentioning

confidence: 99%

“…Examples of errors are a hang, livelocks and deadlocks, logical errors in the memory subsystem blocks, as well as errors associated with the incorrect or untimely updates of the cache or memory states. Also in publication [4], an approach of merging threads is proposed, which is based on the fact that the test program generator creates fragments of single-threaded tests for each core and then connects them to a multithreaded test. The process of test fragment building must ensure that a single-threaded test does not change the shared memory areas when it will be parallelized across multiple threads.…”

Section: Stress-functionsmentioning

confidence: 99%

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Ristretto: Random Test Generator for Multicore Microprocessor Cache Coherence Verification

Smirnov

Chibisov

2019

MES

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Modern system-on-chip designs contain multiple computational cores with several levels of caches, as well as a sophisticated memory subsystem. Functional verification of multi-core microprocessor models is known to be a big challenge. There are different approaches for memory subsystem and cache coherence controllers verification but an automated functional test generation strategy is the most commonly used in the industry. In this paper, the technique of automated multi-core test generation is proposed. It can be applied for cache coherence and memory subsystem check in a top-level multi-core RTLmodel simulation. Moreover, the presented test generator can be very effective in generating test scenarios for FPGAprototypes of SoC being designed. In this paper, we also give a detailed description of the random test generator itself and the capabilities of generated test cases. The proposed test generator got its name Ristretto due to the similarity of the word Ristretto with the abbreviation formed from the words "random instruction sequence" (RIS), and the word "threads" (and because ristretto is so concentrated and intense). Some self-checking validation approaches are suggested to obtain correct responses in FPGA-based verification (postsilicon validation). In the paper, we also discuss the bugmasking problem in post-silicon random instruction tests that arises due to limited observability.

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