Advances in Software Pipelining

Rong, Hongbo; Govindarajan, Raghav

doi:10.1201/9781420043839.ch20

Cited by 2 publications

(2 citation statements)

References 79 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Software pipelining schedules the instructions of multiple iterations of a loop body simultaneously to increase the amount of available instruction-level parallelism. Typically, software pipelining is applied to inner-most loops consisting of single basic blocks although extensions are proposed to deal with larger structures [139,Section 20.4]. Similarly to other instruction scheduling approaches, the input is represented by a DG, which in the case of software pipelining is extended with dependencies across iterations (called loop-carried dependencies).…”

Section: Software Pipeliningmentioning

confidence: 99%

“…In addition, Appendices A and B review and classify (Tables 5 and 7) register pressure-aware instruction scheduling and integrated approaches to the three compiler back-end tasks. The paper complements available surveys of register allocation [91,122,128,133,134], instruction scheduling [2,42,68,136,139], and integrated code generation [97], whose focus tends to be on heuristic approaches.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Survey on Combinatorial Register Allocation and Instruction Scheduling

Lozano

Schulte

2019

ACM Comput. Surv.

View full text Add to dashboard Cite

Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler. In the past three decades, combinatorial optimization has emerged as an alternative to traditional, heuristic algorithms for these two tasks. Combinatorial optimization approaches can deliver optimal solutions according to a model, can precisely capture trade-offs between conflicting decisions, and are more flexible at the expense of increased compilation time. This article provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that are most applied in this context: integer programming, constraint programming, partitioned Boolean quadratic programming, and enumeration. Researchers in compilers and combinatorial optimization can benefit from identifying developments, trends, and challenges in the area; compiler practitioners may discern opportunities and grasp the potential benefit of applying combinatorial optimization.

show abstract

Section: Software Pipeliningmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Survey on Combinatorial Register Allocation and Instruction Scheduling

Lozano

Schulte

2019

ACM Comput. Surv.

View full text Add to dashboard Cite

show abstract

Register allocation for software pipelined multidimensional loops

Rong

Douillet

Gao

2008

ACM Trans. Program. Lang. Syst.

View full text Add to dashboard Cite

This article investigates register allocation for software pipelined multidimensional loops where the execution of successive iterations from an n -dimensional loop is overlapped. For single loop software pipelining, the lifetimes of a loop variable in successive iterations of the loop form a repetitive pattern. An effective register allocation method is to represent the pattern as a vector of lifetimes (or a vector lifetime using Rau's terminology [Rau 1992]) and map it to rotating registers. Unfortunately, the software pipelined schedule of a multidimensional loop is considerably more complex and so are the vector lifetimes in it. In this article, we develop a way to normalize and represent the vector lifetimes, which captures their complexity, while exposing their regularity that enables a simple solution. The problem is formulated as bin-packing of the multidimensional vector lifetimes on the surface of a space-time cylinder. A metric, called distance, is calculated either conservatively or aggressively to guide the bin-packing process, so that there is no overlapping between any two vector lifetimes, and the register requirement is minimized. This approach subsumes the classical register allocation for software pipelined single loops as a special case. The method has been implemented in the ORC compiler and produced code for the IA-64 architecture. Experimental results show the effectiveness. Several strategies for register allocation are compared and analyzed.

show abstract

Advances in Software Pipelining

Cited by 2 publications

References 79 publications

Survey on Combinatorial Register Allocation and Instruction Scheduling

Survey on Combinatorial Register Allocation and Instruction Scheduling

Register allocation for software pipelined multidimensional loops

Contact Info

Product

Resources

About