Advances in the design of the TOTEM neurochip

Lee, Peter; Lazzizzera, I.; Zorat, Alessandro; Sartori, A.; Tecchiolli, Giampietro

doi:10.1016/s0168-9002(97)00063-6

Cited by 10 publications

(3 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For the architecture in this paper both the weights and data have been calculated with between 4 and 8 bits of fractional precision for the logarithmic representation. As shown in [3], this is sufficient for acceptable performance of the TOTEM neural network. The paper shows that it is efficient to implement a classical MAC unit using the hybrid-LNS method at these levels of precision in a modern FPGA.…”

Section: Introductionmentioning

confidence: 93%

“…The performance of the TOTEM system was compared favourably with other benchmark architectures by Lindsay et al [13]. A further change to the TOTEM architecture was proposed in [3] where hybrid-log techniques were used to build a high speed, low-power MAC unit. A test device was developed and is shown in Figure 3.…”

Section: The Totem Neural Network Architecturementioning

confidence: 99%

“…In recent years the original TOTEM architecture has undergone a series of enhancements from its original custom VLSI implementation and has recently been ported onto FPGA technology [2]. In [3] Lee et al considered the possibility of using logarithmic signal processing for implementing a "multiplierless" MAC unit for the TOTEM architecture and showed that this method had potential for providing faster computation and lower power dissipation than the equivalent linear arithmetic MAC unit used in the original devices. Theoretical simulations confirmed that the use of low-precision logarithmic representations for the weights and for performing the signal processing did not impact significantly on the performance of version of the MAC unit has subsequently been designed [4].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

LogTOTEM: A Logarithmic Neural Processor and its Implementation on an FPGA Fabric

Lee

Costa

McBader

et al. 2007

2007 International Joint Conference on Neural Networks

View full text Add to dashboard Cite

This paper describes the design of a neural network architecture optimised for use with the Reactive Tabu Search (RTS) training algorithm. The neural network is built using the hybrid-Logarithmic Number System (hybrid-LNS) instead of the traditional fixed-point methods for the multiplyaccumulate (MAC) unit contained in each neuron. The circuits have been designed and implemented using between 4 and 8 bits of fractional precision for the logarithmic representation of the weights and the data. The architecture is based on the existing TOTEM VLSI chip and contains 32 neurons each having a 256 x 10-bit weight RAM. The device has been implemented on a Virtex XCV600 device where it consumed less 6025 slices with 4 bits of fractional precision of the logarithms and 6280 slices with 5 bits of fractional precision. At 4-bits This represents a (45%) reduction in logic resources required by the neuron array and an overall reduction of 10% of the FPGA resources when compared to the SoftTOTEM device built using the same technology.

show abstract

Section: Introductionmentioning

confidence: 93%

Section: The Totem Neural Network Architecturementioning

confidence: 99%