Advancing high performance heterogeneous integration through die stacking

Madden, Lachlan; Wu, Ephrem; Kim, Nam Hoon; Banijamali, Bahareh; Abugharbieh, Khaldoon; Ramalingam, Suresh; Wu, Xin

doi:10.1109/esscirc.2012.6341246

Cited by 14 publications

(7 citation statements)

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“…At the other extreme, a stack may one day be composed of different dies manufactured by different companies for a "competitive socket" approach [1], [20]. In this case, the stack could consist of different types of dies-processors, memories, DSPs, ASICs, FPGAs, and analog dies [21], [22]. In addition, silicon interposers may be placed between dies to allow appropriate TSV connections.…”

Section: B What Kinds Of Dies Are Present In a 3d Stack?mentioning

confidence: 99%

Repairing a 3-D Die-Stack Using Available Programmable Logic

Nepal

Alhelaly

Dworak

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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3D die-stacks hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3D stack are leading to yield issues and slowing the large scale manufacturing of these devices. In many cases, a single defective die will kill the entire stack. To help mitigate this issue, we explore the possibility of repairing a stack that contains a defective die by utilizing an FPGA that has already been included in the stack for other purposes, such as performance enhancement. Specifically, we propose bypassing the defective portion of a non-programmable die by replacing the defective functionality with functionality on the FPGA. In this article, we discuss what additional logic must be added to an ASIC die to allow such a bypass to occur. We then show through detailed simulation of a 2.5D Xilinx FPGA how bypassing of logic can be achieved and throughput maintained even when the two different dies involved operate at different frequencies.Finally, we explore the performance of this technique in a superscalar, out-of-order processor, where different functional units are marked for replacement. Our simulation results show that not only can we salvage a device that would otherwise have to be discarded, but creating multiple copies of the defective partition in the FPGA can allow us to regain performance even when the latency of the units in the FPGA is longer than that of the original defective copy.

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Section: B What Kinds Of Dies Are Present In a 3d Stack?mentioning

confidence: 99%

Repairing a 3-D Die-Stack Using Available Programmable Logic

Nepal

Alhelaly

Dworak

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In this experimentation, we consider clusters arity 8 and LUT size 4 and a unidirectional routing network. The increased interposer delay is fixed to 1ns as reported [18,19]. To compensate the routing difficulty in crossing the interposer, we use 60% of long wires segment with span of 3.…”

Section: D Moc-based Fpga Delay Analysismentioning

confidence: 99%

“…Toward robust FPGA, the recent product demonstrations from major FPGA manufactures revels the adoption of silicon interposer based 2.5D integration scheme, where TSVs are incorporated in passive silicon interposer [5,6]. The 2.5D multi-FPGA silicon integration is able to improve the manufacturing of high density FPGA, however failed to improve the performance of the FPGA chip [7].…”

Section: Introductionmentioning

confidence: 99%

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation

Chtourou

Abid

Pangracious

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

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International audienceIn this study, we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Clusters (MoC) topology for FPGA architecture design. Design and experimental setup is developed to demonstrate the improvement in performance, power and area of 2.5D and 3D MoC-based FPGA architecture. MoC starts with a mesh of nodes and builds a separate hierarchical network along each row and column in the mesh. To obtain the optimal MoC programmable interconnect structure with high performance and density, the routing architecture of the 2D MoC-based FPGA is modified to include long routing segments which span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, we can design and build 2.5D and 3D high density MoC FPGAs. To design 3D MoC-based FPGAs, we cut the 2D MoC FPGA into two equal FPGA dies and we adjust the long wire span factor to connect the two dies. Then, these long wire segments are converted as 3D through silicon via (TSV) technology. To design 2.5D interposer based multi-FPGA architecture, we use the same principle of cuts and we adjust the long wires span to remain within die connections. However, we apply constraints at cutline location to reduce the die to die interposer connections. A 3D physical design CAD for MoC-based FPGA is developed using Global Foundries 130nm technology node modified to use TSV designs from Tezzaron Semiconductor inc. Using our 3D design and simulation tool flow developed for MoC-based FPGA, we demonstrate that the speed, power and area of 3D MoC-based FPGA architecture are improved respectively by 35%, 21% and 47% in comparison to 2D MoC-based FPGA

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“…By coordinated efforts of new architecture, software, technology, design, testing and business operations, in 28nm 7-Series ® FPGA included both homogeneously and heterogeneously integrated 3D-IC products which extended "more-than-Moore" logic capacity (Fig 2). These products started in sampling in later 2011 and went in volume production 2012 and 2013 [1][2][3].…”

Section: Introduction -Xilinx' 3d-icsmentioning

confidence: 99%

3D-IC FPGA: KGD, DFT and build-in FA capabilities

2015

2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits

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Among many challenges in the development of 3D-IC products, cost is one of the top concerns. Within cost elements, known-good-die (KGD) and 3D-IC integration yield, are among a few biggest impacting factors. In order to achieve high 3D-IC integration yield, build-in self-repairing, design-for-testing (DFT), diagnostic, and failure analysis (FA) capabilities, are very important elements of 3D-IC FPGA technology and product development and manufacturing.

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Advancing high performance heterogeneous integration through die stacking

Cited by 14 publications

References 0 publications

Repairing a 3-D Die-Stack Using Available Programmable Logic

Repairing a 3-D Die-Stack Using Available Programmable Logic

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation

3D-IC FPGA: KGD, DFT and build-in FA capabilities

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