AER-SRT: Scalable spike distribution by means of synchronous serial ring topology address event representation

Abstract

Given the massive number of interconnects in Spiking Neural Networks (SNNs), distributing spikes effciently becomes a critical issue for the efficient hardware emulation of large-scale SNNs. In this work, the AER-SRT (Address Event Representation over Synchronous Serial Ring Topology) architecture for spike transmission is proposed. AER-SRT is a light, easily scalable, packet-based solution implemented with high-speed serial link for multi-chip SNN communication. The channel uses a unidirectional, point-to-point connection between nodes, which provides a high transmission speed. Events (spikes) are distributed among all the nodes in a ring-topology pipeline fashion and the synchronous AER guarantees a collision-free scheme. The fast speed and efficient channel usage limits the spike distribution time to values that allow real-time operation for network sizes that can be calculated with simple design equations. Also, in the proposed communication protocol there is no specific or master node, so new nodes can be added to the ring by simply modifying two configuration parameters. As a proof of concept, a prototype of the architecture has been implemented and tested on FPGA development boards.

Bio-inspired unsupervised learning of visual features leads to robust invariant object recognition

“…Our model could be efficiently implemented in hardware, for example using address event representation (AER) [50,51,52,53]. With AER, the spikes are carried as addresses of sending or receiving neurons on a digital bus.…”

SNAVA—A real-time multi-FPGA multi-model spiking neural network simulation architecture

“…All the above has been taken into account in SNAVA and it has been designed to support all the SNN models that follow the conventional threshold-based spiking approach, right from the simplest IF model to the complex Iglesias and Villa with STDP [25], where the communication between neurons is only through spikes. In addition, SNAVA is a scalable architecture and has the flexibility to be implemented into several chips forming a system in any topology of user's choice [26]. The design of SNAVA architecture was based on three key ideas that have contributed to simulate large-scale SNN models at high processing speeds and communication speeds.…”

“…Therefore, several neurons could be simulated in that time by using the same array. the AER bus the broadcasted addresses of the neurons that spiked [26] and generates matches if the PE has synaptic connections to that neuron. This match is stored in the position that corresponds to the synaptic connection in the spike register.…”

“…d) Spike generation -This module is in charge of sending spikes that are produced during the synaptic-neural processing phase to the AER control [26] in order to carry out the spike distribution phase. The main feature of this module is to inform the AER control the details of the neurons that have fired by sending the address of the neuron to it.…”

“…The network can be mapped on several FPGA boards (SNAVA boards). The number of SNAVA boards to be connected to the ring network [26] is indicated in the "SNAVA Boards" text box, as shown in Fig. A1.…”