Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel architecture is implemented in modern Field-Programmable Gate Arrays (FPGAs) devices to provide high performance execution and flexibility to support large-scale SNN models. Flexibility is defined in terms of programmability, which allows easy synapse and neuron implementation. This has been achieved by using a special-purpose Processing Elements (PEs) for computing SNNs, and analyzing and customizing the instruction set according to the processing needs to achieve maximum performance with minimum resources. The parallel architecture is interfaced with customized Graphical User Interfaces (GUIs) to configure the SNN's connectivity, to compile the neuron-synapse model and to monitor SNN's activity. Our contribution intends to provide a tool that allows to prototype SNNs faster than on CPU/GPU architectures but significantly cheaper than fabricating a customized neuromorphic chip. This could be potentially valuable to the computational neuroscience and neuromorphic engineering communities.

Given the massive number of interconnects in Spiking Neural Networks (SNNs), distributing spikes effciently becomes a critical issue for the efficient hardware emulation of large-scale SNNs. In this work, the AER-SRT (Address Event Representation over Synchronous Serial Ring Topology) architecture for spike transmission is proposed. AER-SRT is a light, easily scalable, packet-based solution implemented with high-speed serial link for multi-chip SNN communication. The channel uses a unidirectional, point-to-point connection between nodes, which provides a high transmission speed. Events (spikes) are distributed among all the nodes in a ring-topology pipeline fashion and the synchronous AER guarantees a collision-free scheme. The fast speed and efficient channel usage limits the spike distribution time to values that allow real-time operation for network sizes that can be calculated with simple design equations. Also, in the proposed communication protocol there is no specific or master node, so new nodes can be added to the ring by simply modifying two configuration parameters. As a proof of concept, a prototype of the architecture has been implemented and tested on FPGA development boards.