Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High- $\kappa$/Metal-Gate nFinFETs for High-Performance Logic Applications

Maitra, K.; Khakifirooz, A.; Kulkarni, P.; Basker, V.; Faltermeier, J.; Jagannathan, H.; Adhikari, Hemant; Yeh, Chun-Chen; Klymko, N.; Saenger, K. L.; Standaert, T.; Miller, R.L.; Doris, B.; Paruchuri, Vamsi; McHerron, D.; O’Neil, James P.; Leobundung, E; Bu, H.

doi:10.1109/led.2011.2126556

Cited by 27 publications

(5 citation statements)

References 8 publications

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“…In order to verify accuracy, the models are fitted with measurement data from industrial publications and parameters such as subthreshold slope, DIBL, etc., are plotted with the PTM-MG trends [13,16,[19][20][21][22][23][24][25][26].…”

Section: Ptm-mg Evaluationmentioning

confidence: 99%

Exploring sub-20nm FinFET design with predictive technology models

Sinha

Yeric

Chandra

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

266

132

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Predictive MOSFET models are critical for early stage designtechnology co-optimization and circuit design research. In this work, Predictive Technology Model files for sub-20nm multi-gate transistors have been developed (PTM-MG). Based on MOSFET scaling theory, the 2011 ITRS roadmap and early stage silicon data from published results, PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap.

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Section: Ptm-mg Evaluationmentioning

confidence: 99%

Exploring sub-20nm FinFET design with predictive technology models

Sinha

Yeric

Chandra

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

266

132

View full text Add to dashboard Cite

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“…Generally, the criteria of acceptable SCE for short channel regime are considered below 100 mV. 19) In Fig. 5, according to the criteria, the maximum ratio of W=L G for SOI tri-gate transistors is around 1.25.…”

Section: Resultsmentioning

confidence: 99%

Advanced 10 nm Width Silicon-on-Insulator Tri-Gate Transistors with NO Annealing of Gate Oxide Using Optimized Novel Silicon-on-Insulator Realization Technology

Kim

Bae

et al. 2012

Jpn. J. Appl. Phys.

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An advanced method of the novel silicon-on-insulator (SOI) realization technology is proposed for the fabrication of SOI tri-gate transistors. Using the new method, 10 nm width SOI tri-gate transistors are successfully fabricated on standard Si bulk wafers, and result in excellent electrical characteristics after optimizing the processing parameters. Among others, low-cost and high manufacturability to fabricate SOI tri-gate transistors are advantages of the proposed method. Formed on the standard Si bulk wafer process, the SOI tri-gate transistors with gate length (L G) of 45 nm have reasonable threshold voltage (V TH) of 0.18 V and showed the enhanced current drivability up to 20%. They also demonstrated good short channel effect immunities: sub-threshold swing (SS) and drain induced barrier lowering (DIBL) were 70 mV/dec and 24 mV/V, respectively. Therefore, the novel method for the novel SOI realization technology proposed in this work will be one of the candidates for the scaling-down strategy in the future.

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“…Although nanowire (NW) transistors with excellent electrostatic control have been fabricated [1][2][3], several key challenges remain to achieve high-speed circuits based on CMOS NW technology. As a result, substrate strain engineering utilizing biaxial strain substrates such as sSOI for n-FET has been proposed as a promising solution for advanced technology nodes [4][5][6]. In view of high performance hybrid CMOS integrating strained-Si channel for n-FET and strained-SiGe channel for p-FET, it becomes necessary to study the advantages of uniaxial strain in deeply scaled n-FET NWs.…”

Section: Introductionmentioning

confidence: 99%

Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Barraud¹,

Laviéville²,

Tabone³

et al. 2014

2014 15th International Conference on Ultimate Integration on Silicon (ULIS)

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High-performance strainedSilicon-OnInsulator (sSOI) nanowire (NW) transistors with gate length and NW width down to 15 nm are reported. We demonstrate sSOI π-Gate n-FET NWs with I ON current of 1410 μA/μm (when I OFF = 70 nA/μm) at V DD =0.9V and a good electrostatic immunity (DIBL = 140 mV/V, SS SAT = 76 mV/dec). Effectiveness of sSOI substrates for n-FETs is shown with an I ON improvement up to +40% at short gate lengths. More generally, size-and orientation-dependent strain impact on electron and hole transport in long and short channel π-Gate (s)SOI NW transistors is systematically studied.

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Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High- $\kappa$/Metal-Gate nFinFETs for High-Performance Logic Applications

Cited by 27 publications

References 8 publications

Exploring sub-20nm FinFET design with predictive technology models

Exploring sub-20nm FinFET design with predictive technology models

Advanced 10 nm Width Silicon-on-Insulator Tri-Gate Transistors with NO Annealing of Gate Oxide Using Optimized Novel Silicon-on-Insulator Realization Technology

Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

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