Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Barraud, S.; Laviéville, Romain; Tabone, C.; Allain, F.; Cassé, M.; Samson, M.-P.; Maffini-Alvarro, V.; Vinet, M.

doi:10.1109/ulis.2014.6813907

Cited by 16 publications

(5 citation statements)

References 11 publications

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“…the devices are fabricated using nanowires on Si-oninsulator (Soi) complementary metaloxide semiconductor technology [27]. An experiment with a short-channel HJFET at T 3.5 K. c (a) A "DC" differential conductance "map."…”

Section: Dual-port Rfr For Nanoscale Si Metal-oxide-semiconductor Setmentioning

confidence: 99%

Dual-Port Reflectometry Technique: Charge identification in nanoscaled single-electron transistors

Orlov

Fay

Snider

et al. 2015

IEEE Nanotechnology Mag.

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Radio-fRequency Reflectometry (RfR) is a technique that was developed to characterize the properties of transmission lines by observing reflected waveforms. today, it is widely used in a variety of applications, ranging from the detection of faulty wires in cables [1] and objects buried in the ground [2] to soil moisture detectors [3] and the measurement of dielectric properties of blood [4]. Recently, one important application of this technique, which requires a very small amount of applied power, was developed for the characterization of electronic nanostructures [5]. in this implementation, a microwave radio-frequency (Rf) signal is sent to a resonator coupled to the specimen to be studied. if in a specimen the change of some external parameter (e.g., gate voltage) leads to a change of an active [figure 1(a)] or a reactive (typically, capacitive) load [ figure 1(b)] to the resonator, the self-resonance is affected, resulting in a change of magnitude [figure 2(a)] and phase [figure 2(b)] of the reflected signal. if an impedance matching condition is achieved, the modification of the specimen parameter (e.g., the increase of its resistance) will lead to a very significant change in the reflection coefficient C [ figure 2(a)]. Here, we discuss two important applications of the RfR technique on nanoscale devices.first, RfR provides a method for fast (<100 ns) and broadband (in excess of 100 mHz) sensing of single-electron transistors (Sets) [5] and quantum point contacts (qPcs) [6], which are essential readout elements for promising new technologies such as spin quantum bits [7]- [9]. By contrast, the traditional methods of probing these types of devices by measuring changes in their conductance or resistance suffer from very limited bandwidth (<1 mHz) due to the high impedance of the devices and parasitic input capacitance of the sensing amplifier. in an

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Section: Dual-port Rfr For Nanoscale Si Metal-oxide-semiconductor Setmentioning

confidence: 99%

Dual-Port Reflectometry Technique: Charge identification in nanoscaled single-electron transistors

Orlov

Fay

Snider

et al. 2015

IEEE Nanotechnology Mag.

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“…Different studied are already done in this NW devices, in [8][9][10][11][12] the performance of NW with respect to strain on mobility was studied, the low-frequency noise was analyzed in [13,14], crystallographic orientation [10,13,14] and scalability effects [4,8,15] are also studied.…”

Section: Introductionmentioning

confidence: 99%

Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

Itocazu

Almeida

Sonnenberg

et al. 2019

Semicond. Sci. Technol.

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This paper presents a comparison between nMOS and pMOS Ω-Gate Nanowire for different channel width (W NW ) down to 10 nm as a function of the large back gate bias variation (from +20 to −20 V) experimentally and by simulation. The main digital and analog parameters are analyzed in these devices as threshold voltage, subthreshold swing (SS), transconductance, transistor efficiency, Early Voltage and intrinsic voltage gain for transistor channel width from 220 nm down to 10 nm. It is shown that narrow channel devices (W NW =10 nm) present a small variation on the analyzed parameters as a function of back gate voltage due to stronger electrostatic control between gate and channel considering that they are effectively working like a gate-all-around devices. In general, all the nMOS parameters presents better results compared to pMOS due to the mobility enhancements. For wider devices (W NW =220 nm), it depends on the back interface condition. For a large enough back gate bias that tends to create a back interface conduction (+20 V for nMOS and −20 V for pMOS), the SS degrades from 61 mV dec −1 (W NW =10 nm) to 68 mV dec −1 (W NW =220 nm). However for a large enough back gate bias that induces a non-conduction region (tends to accumulation) at back interface (−20 V for nMOS and +20 V for pMOS) the SS changes from 60 to 62 mV dec −1 at the same W NW range, which is a very acceptable results. Additionally, the drain current (I ON ) and transconductance (linear and saturation regions) increase for this back gate bias condition (tends to accumulation), working almost like a pseudo nanosheet device for these parameters, avoiding also the parasitic conduction at the back interface. However, in spite of the intrinsic voltage gain is almost independent of the back gate bias, it improves of at least 10 dB for narrow devices due to the higher Early voltage and almost similar transistor efficiency than the wider ones.

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“…The use of carrier mobility boosters, such as the implementation of different materials, mechanical stress and rotated substrates, demonstrated to be an important ally to the continuity of the CMOS roadmap, so multiple gate MOSFETs would be able to fulfill higher drive current requests imposed by the International Technology Roadmap for Semiconductors (ITRS). While the use of compressive and tensile stress can enhance holes and electrons mobility, respectively [5], [100]-orientated channel can boost n-type NWs current due to higher electrons mobility along (100) sidewalls [6].…”

Section: Introductionmentioning

confidence: 99%

Electrical characterization of vertically stacked p-FET SOI nanowires

Paz

Cassé

Barraud

et al. 2018

Solid-State Electronics

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This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [110]-and [100]-oriented channels, as a function of both fin width (WFIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [110]-in comparison to [100]-oriented NWs due to higher holes mobility contribution in (110) plan. Improvements obtained on ION/IOFF by reducing WFIN are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [110]-and [100]-oriented NWs, respectively.

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Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Cited by 16 publications

References 11 publications

Dual-Port Reflectometry Technique: Charge identification in nanoscaled single-electron transistors

Dual-Port Reflectometry Technique: Charge identification in nanoscaled single-electron transistors

Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

Electrical characterization of vertically stacked p-FET SOI nanowires

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