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This paper presents an analysis of the Ground Plane (GP) implantation and silicon film thickness influences on Ultra Thin Buried Oxide (UTBOX) SOI MOSFETs. The results obtained experimentally and by simulations, considering the GP implantation, show that the device must have a GP implantation higher than 1x10 18 cm -3 in order to eliminate the substrate effect. In spite of the fact that the substrate influence on the drain current is negligible with a high GP concentration, the coupling between front and back interface increases for thinner silicon films.

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An analysis of the temperature influence on the substrate effect of short channel Ultra Thin Body and BOX (UTBB) SOl nMOSFETs with and without Ground Plane (GP) implantation is presented. This study was done from room temperature up to 200·C. The theoretical model was applied and the results are in agreement with experimental and simulation data. The data shows a kink in the drain current as a function of back-gate voltage due to the substrate potential drop when the ground plane is not present. The ground plane reduces the substrate potential drop, but increases the potential drop over the gate and buried oxides. The maximum difference between V GB with and without GP decreases for high temperature.

This paper presents an analysis of the temperature influence on Ultra Thin Body and Box (UTBB) SOI nMOSFETs with and without Ground Plane (GP) implantation and different silicon film thickness. The results obtained experimentally and by simulations show a kink in the drain current as a function of back-gate voltage due to the substrate potential drop when the ground plane is not present. The ground plane reduces the substrate potential drop, but increases the potential drop at gate and buried oxides. This study was done from room temperature up to 200oC.