2015 30th Symposium on Microelectronics Technology and Devices (SBMicro) 2015
DOI: 10.1109/sbmicro.2015.7298114
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Ground Plane influence on UTBB SOI nMOSFET analog parameters

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Cited by 3 publications
(4 citation statements)
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“…Device with t Si = 6 nm + High-κ (HK / t Si =6) presents the lower percentage difference comparing devices with and without GP, as shown in Table V. In all cases, devices without GP present better results, due to the lower drain electrical field penetration, in agreement with the tendency observed in [13].…”
Section: A Ground Plane Influence Varying the Back Gate Voltagesupporting
confidence: 82%
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“…Device with t Si = 6 nm + High-κ (HK / t Si =6) presents the lower percentage difference comparing devices with and without GP, as shown in Table V. In all cases, devices without GP present better results, due to the lower drain electrical field penetration, in agreement with the tendency observed in [13].…”
Section: A Ground Plane Influence Varying the Back Gate Voltagesupporting
confidence: 82%
“…The difference between gm S AT of devices without GP and with GP, shown in figure 8, is related with the strong coupling (supercoupling) between front and back interfaces [13] as mentioned in the previous section. However, in devices with L=70 nm, the influence of the drain electrical field penetration is higher than the supercoupling between front and back interfaces.…”
Section: A Ground Plane Influence Varying the Back Gate Voltagementioning
confidence: 68%
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