2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) 2016
DOI: 10.1109/aspdac.2016.7428082
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Aging-aware high-level physical planning for reconfigurable systems

Abstract: Due to advanced silicon technology, reconfigurable system-on-chip devices such as FPGAs are increasingly becoming sensitive to aging effects. This paper presents a high-level physical planning with reconfiguration strategy in order to mitigate the aging-induced delay degradation in FPGA resources. The proposed solution is an offline framework composed of an agingaware floorplanner coupled with a proactive aging-aware reconfiguration policy which generates checkpoints aperiodically for runtime reconfiguration. … Show more

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Cited by 19 publications
(2 citation statements)
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“…Similarly, ref. [108] presented a reliability-aware floorplanning methodology along with delay-based aging estimation and run-time reconfiguration. A joint mitigation methodology using DPR, aimed at both soft errors and permanent faults in FPGAs was proposed by [109].…”
Section: Reliability Management In Reconfigurable Architecturesmentioning
confidence: 99%
“…Similarly, ref. [108] presented a reliability-aware floorplanning methodology along with delay-based aging estimation and run-time reconfiguration. A joint mitigation methodology using DPR, aimed at both soft errors and permanent faults in FPGAs was proposed by [109].…”
Section: Reliability Management In Reconfigurable Architecturesmentioning
confidence: 99%
“…This performance degradation, referred to as transistor aging, is the result of several physical mechanisms (negative bias temperature instability (NBTI), electromigration (EM), and more), and is generally a greater concern when scaling to smaller technology nodes [23]. Fieldprogrammable gate arrays (FPGAs) are not immune to this efect, and several studies have measured how FPGA performance is afected by transistor aging [1,6,11].…”
Section: Introductionmentioning
confidence: 99%