Aging statistics based on trapping/detrapping: Silicon evidence, modeling and long-term prediction

Velamala, Jyothi; Sutaria, Ketul B.; Satō, Takashi; Cao, Yu

doi:10.1109/irps.2012.6241795

Cited by 38 publications

(26 citation statements)

References 11 publications

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“…The change of threshold voltage (∆V th ) follows a power law function of aging time [11]. In comparison, the T-D model involves a charge trapping/detrapping, and ∆V th follows a logarithmic function of the stress time [21]. Recent work reveals that there exists a significant amount of permanent degradation from the NBTI effect, and a new kind of Hydrogen Release (H-R) model has been proposed which can explain this phenomenon [22,23].…”

Section: Nbti-induced Transistor Agingmentioning

confidence: 99%

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NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Sun

Yang

et al. 2017

Algorithms

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As technology scales, negative bias temperature instability (NBTI) becomes one of the primary failure mechanisms for Very Large Scale Integration (VLSI) circuits. Meanwhile, the leakage power increases dramatically as the supply/threshold voltage continues to scale down. These two issues pose severe reliability problems for complementary metal oxide semiconductor (CMOS) devices. Because both the NBTI and leakage are dependent on the input vector of the circuit, we present an input vector control (IVC) method based on a linear programming algorithm, which can co-optimize circuit aging and power dissipation simultaneously. In addition, our proposed IVC method is combined with the supply voltage assignment technique to further reduce delay degradation and leakage power. Experimental results on various circuits show the effectiveness of the proposed combination method.

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Section: Nbti-induced Transistor Agingmentioning

confidence: 99%

“…For example, the R-D model has been verified to be effective for a moderate to very long stress time [24]. In contrast, the T-D model is capable of predicting ultrafast measurement data more precisely; moreover, the T-D model can also capture the aging variability of the NBTI effect [21,25,26].…”

Section: Nbti-induced Transistor Agingmentioning

confidence: 99%

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Sun

Yang

et al. 2017

Algorithms

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“…This phenomenon is similar to the random V th variation induced by the number and the placement of dopant atoms in the channel, known as the random dopant fluctuation (RDF) effect. The general framework of BTI variation has been proposed by Stewart in [17], where the number of broken bonds N IT in the channel has been modeled as a Poisson random variable. Under this assumption, N IT satisfies the following:…”

Section: Modeling Bti-induced Cmos Device Agingmentioning

confidence: 99%

Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

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With CMOS technology aggressively scaling towards the 22-nm node, modern FPGA devices face tremendous aging-induced reliability challenges due to bias temperature instability (BTI) and hot carrier injection (HCI). This paper presents a novel anti-aging technique at the logic level that is both scalable and applicable for VLSI digital circuits implemented with FPGA devices. The key idea is to prolong the lifetime of FPGA-mapped designs by strategically elevating the V DD values of some LUTs based on their modular criticality values. Although the idea of scaling V DD in order to improve either energy efficiency or circuit reliability has been explored extensively, our study distinguishes itself by approaching this challenge through an analytical procedure, therefore being able to maximize the overall reliability of the target FPGA design by rigorously modeling the BTI-induced device reliability and optimally solving the V DD assignment problem. Specifically, we first develop a systematic framework to analytically model the reliability of an FPGA LUT (look-up table), which consists of both RAM memory bits and associated switching circuit. We also, for the first time, establish the relationship between signal transition density and a LUT's reliability in an analytical way. This key observation further motivates us to define the modular criticality as the product of signal transition density and the logic observability of each LUT. Finally, we analytically prove, for the first time, that the optimal way to improve the overall reliability of a whole FPGA device is to fortify individual LUTs according to their modular criticality. To the best of our knowledge, this work is the first to draw such a conclusion.

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“…The absolute value of the transistor threshold voltage is increased over time because of transistor aging (such as NBTI, PBTI, and HCI). Therefore, it leads to decrease in the driving currents of transistors and in turn degradation of transistors delay over time [26][27][28][29]. PVT variations, and workload-dependent logic probability (LP) and toggling rate (TR) of transistors considerably can impact the pace of transistor aging [30,13,29].…”

Section: Introductionmentioning

confidence: 99%

Cross-layer custom instruction selection to address PVTA variations and soft error

Farahani

Safari

2015

Microelectronics Reliability

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Aging statistics based on trapping/detrapping: Silicon evidence, modeling and long-term prediction

Cited by 38 publications

References 11 publications

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Optimally Fortifying Logic Reliability through Criticality Ranking

Cross-layer custom instruction selection to address PVTA variations and soft error

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