We consider an example with the following specifications: Si relative permittivity e r1 ¼ 11.9, Si conductivity r 1 ¼ 7.4S/m, lossless SiO 2 e r2 ¼ 4, Cu r c ¼ 5.8e7 S/m, a ¼ 10 lm Figure 4(a) presents the insertion losses of a corner (port 1) and a via near the center (port 6) in a 4-by-4 coated TSV via array. Figure 4(b) gives the return losses. These results are in good agreement with HFSS simulation. It shows that the center via has better high-frequency performance than the corner via because surrounding vias shield it from radiation.Figures 5(a) and 5(b) present the near end crosstalk at a corner via and a via near the center, respectively. It shows the coupling issues among the TSVs will become significant beyond 15 GHz. The crosstalk at the corner via is much stronger than at vias near the center, because scattered radiation accumulates at the via array boundary. Because of the larger separation of diagonal vias, the diagonal crosstalk is usually weaker than the adjacent crosstalk. The CPU time required to simulate a 4-by-4 TSV via array using Matlab code is 5.89 s for 79 frequency points from 1 to 40 GHz, whereas HFSS simulations took 15 h and 43 min for the same structure. All data were generated using an Intel Xeon 2.93G Quad-core processor. The results of these two methods agree well, except small differences below 5 GHz. We will use a quasi-static approach to analyze low-frequency behavior in a future study. 2. B. Wu and L. Tsang, Modeling multiple vias with arbitrary shape of antipads and pads in high speed interconnect circuits, IEEE Microwave Wireless Comp Lett 19 (2009), 12-14. 3. B. Wu and L. Tsang, Full-wave modeling of multiple vias using differential signaling and shared antipad in multilayered high speed vertical interconnects, Prog Electromagn Res 97 (2009), 129-139. 4. B. Wu and L. Tsang, Signal integrity analysis of package and printed circuit board with multiple vias in substrate of layered dielectrics, IEEE Trans Adv Packag 33 (2010), 510-516. 5. H. Hasegawa, M. Furukawa, and H.