Algorithm and architecture-level design space exploration using hierarchical data flows

Peixoto, H.P.; Jacome, Margarida F.

doi:10.1109/asap.1997.606833

Cited by 10 publications

(13 citation statements)

References 19 publications

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“…Our algorithm is currently being implemented in Sky [15], a tool for assisting algorithm and architecture-level design space exploration during system level design. We also plan to implement the proposed algorithm on a reuse tool currently on its preliminary stage of development.…”

Section: Discussionmentioning

confidence: 99%

“…In general a hierarchical high-level system model comprises a variety of nodes and arc's representing computations and flow of control constructs, including branching, looping, and possible synchronization requirements, see e.g., [9,7,4,1,15]. Rather than formally defining such a framework we will exhibit some cases that arise and the manner in which they are reduced to a corresponding DAG.…”

Section: Hierarchical Representations and Reductions To Directed Acycmentioning

confidence: 99%

“…For example, for high-level system representations, such as those used in system level and hardware/software codesign, uncertainty may be due to a looping index whose exact initial value is unknown, e.g., data dependent [1,4,7,6,9,15,16]. A number of current system-level models use hierarchy and aggregation as a means of controlling complexity [4,15]. If such approaches are to succeed, and one is to reason efficiently about the required performance of such systems during design space exploration, it will become increasingly critical to capture the performance variability of aggregated system elements.…”

Section: Introductionmentioning

confidence: 99%

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Hierarchical algorithms for assessing probabilistic constraints on system performance

Veciana

Jacome

Guo

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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We propose an algorithm for assessing probabilistic performance constraints for systems including components with uncertain delays. We make a case for designing systems based on a probabilistic relaxation of performance constraints, as this has the potential for resulting in lower silicon area and/or power consumption. We consider a concrete example, an MPEG decoder, for which we discuss modeling and assessment of probabilistic throughput constraints.

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Section: Discussionmentioning

confidence: 99%

Section: Hierarchical Representations and Reductions To Directed Acycmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Hierarchical algorithms for assessing probabilistic constraints on system performance

Veciana

Jacome

Guo

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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“…Sciuto et al [104] define affinity metrics for applications towards mappings onto DSPs, ASICs, and general-purpose processors. Peixoto et al [93] define metrics which favor resource sharing. Those metrics guide optimizations towards clusters of similar computations that show high locality.…”

Section: Strategies For Covering the Design Spacementioning

confidence: 99%

“…For a given problem description it must be decided which parts of the specification should be implemented in software and which in hardware. Indicators, such as potential speedups, areaand communication overheads, locality and regularity of computations as, for instance, defined in [93,21], are used for guiding the decision towards hardware or software.…”

Section: Secondary Objectivesmentioning

confidence: 99%

Methods for evaluating and covering the design space during early design development

Gries

2004

Integration, the VLSI Journal

115

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This paper gives an overview of methods used for Design Space Exploration (DSE) at the system-and micro-architecture levels. The DSE problem is considered to be two orthogonal issues: (I) How could a single design point be evaluated, (II) how could the design space be covered during the exploration process? The latter question arises since an exhaustive exploration of the design space by evaluating every possible design point is usually prohibitive due to the sheer size of the design space. We therefore reveal trade-offs linked to the choice of appropriate evaluation and coverage methods. The designer has to balance the following issues: the accuracy of the evaluation, the time it takes to evaluate one design point (including the implementation of the evaluation model), the precision/granularity of the design space coverage, and last but not least the possibilities for automating the exploration process. We also list common representations of the design space and compare current system and micro-architecture level design frameworks. This review thus eases the choice of a decent exploration policy by providing a comprehensive survey and classification of recent related work. It is focused on System-on-a-Chip designs, particularly those used for network processors. These systems are heterogeneous in nature using multiple computation, communication, memory, and peripheral resources.Keywords: Design space exploration, design space pruning, system-level design, micro-architecture design, design frameworks, benchmarking, multi-objective search. NoteWe focus on related work which applies methods in the context of design space exploration. Discussing the theory of optimization methods and the fundamentals of design evaluation is beyond the scope of this survey.

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Advanced Techniques for Embedded Systems Design and Test

1998

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Algorithm and architecture-level design space exploration using hierarchical data flows

Cited by 10 publications

References 19 publications

Hierarchical algorithms for assessing probabilistic constraints on system performance

Hierarchical algorithms for assessing probabilistic constraints on system performance

Methods for evaluating and covering the design space during early design development

Advanced Techniques for Embedded Systems Design and Test

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