Hierarchical algorithms for assessing probabilistic constraints on system performance

Veciana, Gustavo de; Jacome, Margarida F.; Guo, Jian-Huei

doi:10.1145/277044.277113

Cited by 8 publications

(3 citation statements)

References 15 publications

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“…Combinations of QoS and probabilistic constraints have been applied in different areas, such as scheduling of job processes in real time systems, modelling job execution time and interarrival times [8]. Veciana et al formulate the problem of finding combinatorial delays fulfilling probabilistic constraints as a critical path problem for evaluating decoder design models [10]. Further, Felemban et al quantified reachability of packets based on probability distributions of expected destination arrival time, used for routing purposes in wireless networks [11].…”

Section: Related Workmentioning

confidence: 99%

Translation of probabilistic QoS in hierarchical and decentralized settings

Bjurling

Steinert

Gillblad

2011

2011 13th Asia-Pacific Network Operations and Management Symposium

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In this paper we build on methods from probabilistic management for overcoming two issues in the translation of QoS into configurations of network nodes in dynamic, decentralized, and hierarchical networks. First, the inherent uncertainty about node performance in such networks (due to network dynamics) may impede adequate specification of QoS. We suggest how a probabilistic variant of QoS via optimization can be translated into objectives that can be handled with probabilistic management methods. Second, the dynamics of the network may make the interpretation of QoS dependent on the availability of network resources. We use methods from probabilistic management to suggest how the expression of QoS may be restricted in order to be able to ensure the existence of a translation of given QoS. The suggestions are applied to our own network architecture. The aim is to further develop our approach to a viable management solution for cloud computing and virtualized networks.

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Section: Related Workmentioning

confidence: 99%

Translation of probabilistic QoS in hierarchical and decentralized settings

Bjurling

Steinert

Gillblad

2011

2011 13th Asia-Pacific Network Operations and Management Symposium

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“…Some early work has suggested probabilistic analysis [6,14,21,37] for handling WCET variations due to software factors (such as data dependency and history dependency). However, these prior approaches for statistical WCET analysis did not model hardware execution time variations caused by process variations.…”

Section: Related Workmentioning

confidence: 99%

Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions

Mohan

Mueller

2008

2008 IEEE Real-Time and Embedded Technology and Applications Symposium

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Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability analysis provides a firm basis to ensure that tasks meet their deadlines for which knowledge of worst-case execution time (WCET) bounds is a critical piece of information. Static timing analysis techniques are used to derive these WCET bounds. A limiting factor for designing realtime systems is the class of processors that can be used. Typically, modern, complex processor pipelines cannot be used in real-time systems design. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, prefetching, etc., cannot be statically analyzed to obtain tight WCET bounds for tasks. This is caused by the non-determinism of these features, which surfaces in full only at runtime.In this paper, we introduce a new paradigm to perform timing analysis of tasks for real-time systems running on modern processor architectures. We propose minor enhancements to the processor architecture to enable this process. These features, on interaction with software modules, are able to obtain tight, accurate timing analysis results for modern processors. We also briefly present analysis techniques that, combined with our timing analysis methods, reduce the complexity of worst-case estimations for loops. To the best of our knowledge, this method of constant interactions between hardware and software to calculate WCET bounds for out-of-order processors is the first of its kind.

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“…In statistical timing analysis [1] [5][8] [9], the propagation delays of interconnects/cells are modeled as (correlated) random variables with known distribution functions (extracted from layout and process parameters). A statistical timing analyzer based on this statistical delay model can then be used for deriving the probability density functions of the signal arrival times.…”

Section: Introductionmentioning

confidence: 99%

Analysis of performance impact caused by power supply noise in deep submicron devices

Jiang

Cheng

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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The paper addresses the problem of analyzing the performance degradation caused by noise in power supply lines for deep submicron CMOS devices. We first propose a statistical modeling technique for the power supply noise including inductive ∆I noise and power net IR voltage drop. The model is then integrated with a statistical timing analysis framework to estimate the performance degradation caused by the power supply noise. Experimental results of our analysis framework, validated by HSPICE, for benchmark circuits implemented on both 0.25 µ, 2.5 V and 0.55 µ, 3.3 V technologies are presented and discussed. The results show that on average, with the consideration of this noise effect, the circuit critical path delays increase by 33% and 18%, respectively for circuits implemented on these two technologies.

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Hierarchical algorithms for assessing probabilistic constraints on system performance

Cited by 8 publications

References 15 publications

Translation of probabilistic QoS in hierarchical and decentralized settings

Translation of probabilistic QoS in hierarchical and decentralized settings

Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions

Analysis of performance impact caused by power supply noise in deep submicron devices

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