Analysis of performance impact caused by power supply noise in deep submicron devices

Abstract

The paper addresses the problem of analyzing the performance degradation caused by noise in power supply lines for deep submicron CMOS devices. We first propose a statistical modeling technique for the power supply noise including inductive ∆I noise and power net IR voltage drop. The model is then integrated with a statistical timing analysis framework to estimate the performance degradation caused by the power supply noise. Experimental results of our analysis framework, validated by HSPICE, for benchmark circuits implemented on both 0.25 µ, 2.5 V and 0.55 µ, 3.3 V technologies are presented and discussed. The results show that on average, with the consideration of this noise effect, the circuit critical path delays increase by 33% and 18%, respectively for circuits implemented on these two technologies.

Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

“…In deep submicron (DSM) technology, power supply analysis has become increasingly important in predicting the realistic worst-case delays in integrated circuits [1]. Ideally, the gates in the integrated circuit receive the full supply voltage from the …”

Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise

“…Pant et al [11] estimated the voltage variations by convoluting statistically modeled current consumption and the impulse response of a power/ground network. Jiang and Chen [12] first derived the average and standard deviation of all blocks and the correlation coefficients between the blocks, and they then estimated the delay. Kim and Walker [13] focused on the spatial correlation of power supply noise and proposed using principal component analysis (PCA) to model power supply noise.…”

HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery

“…ITH the ultra deep submicron (UDSM) technology, several features of today's chips ( higher operating frequencies, larger number of transistors, smaller feature size, and lower power supply voltage) have pushed the power delivery noise analysis onto the designers' list of high priority concerns [1]- [4]. Basically, the power delivery noise consists of IR drop, drop, and resonance fluctuations.…”