Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions

Abstract

Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability analysis provides a firm basis to ensure that tasks meet their deadlines for which knowledge of worst-case execution time (WCET) bounds is a critical piece of information. Static timing analysis techniques are used to derive these WCET bounds. A limiting factor for designing realtime systems is the class of processors that can be used. Typically, modern, complex processor pipelines cannot be used in real-time systems design. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, prefetching, etc., cannot be statically analyzed to obtain tight WCET bounds for tasks. This is caused by the non-determinism of these features, which surfaces in full only at runtime.In this paper, we introduce a new paradigm to perform timing analysis of tasks for real-time systems running on modern processor architectures. We propose minor enhancements to the processor architecture to enable this process. These features, on interaction with software modules, are able to obtain tight, accurate timing analysis results for modern processors. We also briefly present analysis techniques that, combined with our timing analysis methods, reduce the complexity of worst-case estimations for loops. To the best of our knowledge, this method of constant interactions between hardware and software to calculate WCET bounds for out-of-order processors is the first of its kind.

Merging State and Preserving Timing Anomalies in Pipelines of High-End Processors

“…The CheckerMode infrastructure [9] (Figure 1) provides the means to obtain accurate WCET values for real-time tasks executing on modern processor pipelines. We proposed modifications to the design of embedded processors so that, in addition to the ability to execute software normally (deployment mode), processors are capable of executing in a novel checker mode.…”

“…Snapshots describe the state of the processor captured while performing timing analysis, using our "hybrid" CheckerMode technique [9], to obtain the worst-case execution time for modern processor architectures. It typically consists of the state of each functional unit of the processor at a given point in time (t).…”

“…To perform a merge on the register file state ("RF" from Figure 4) we use a simple technique on each register: (a) If the register value is unchanged across the snapshots, then the merged state will retain that value in the register; (b) If the register value is different, then set the merged value to a Not-A-Number (N aN ) [9]. This is to handle inputdependent values that will not be known until run-time.…”

“…In recent work, we introduced the notion of "hybrid" timing analysis [9] called the CheckerMode infrastructure. This method combines the best features of both static and dynamic analysis to obtain accurate WCET estimates for realtime tasks running on modern microprocessors.…”

Worst-case execution time analysis of security policies for deeply embedded real-time systems

“…This difficulty is more noticeable during the process of determining WCETs of security policies because the actual inputs will not be known until an attack occurs. We also recently introduced a hybrid mechanism [4] which uses hardware/software interactions to accurately gauge WCETs for high-end processors.…”