Algorithm based adaptive parametric testing for outlier detection and test time reduction

Katragadda, Veenadhar; Muthee, Martin; Gasasira, Arthur; Seelmann, Frank; Liao, Jiun-Hsin

doi:10.1109/icmts.2018.8383784

Cited by 8 publications

(5 citation statements)

References 6 publications

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“…The reorder-based Ref [7] and Ref [12] have the same test escape as proposed method, experimental results show that they only focus on test quality, but ignore the test cost. The most similar result is to based Ref [17] method, however, it is the reduction of test time and test escape by increasing a large amount of hardware circuit and area overhead, and the proposed method is completely software-based and does not require any additional hardware overhead. Therefore, it is the best compromise between test escape and test cost of proposed method.…”

Section: The Last Column Ofmentioning

confidence: 93%

“…As we can see, most of previous works are based on minimizing test cost [16], [17], they don't consider the test quality, at the same time, increased hardware overhead leads to increased manufacturing costs, and lacking research on screen out the most effective test patterns, which can provide test cost reduction without increasing the defect level. To bridge this gap and formally show that, in a quest to reduce test cost and increase test quality, the work presented in this paper adopts improved SVMRANK as a pattern selection algorithm which can select the most effective patterns while guaranteeing the test quality.…”

Section: Enormous Defect Detection Overlap Problem Between Test Typesmentioning

confidence: 99%

“…In adaptive test, the test content, test order and pass/fail limits are not fixed as in conventional test, but depend on other test results of the currently or historically tested data (training data), and data analysis that can be used to adjust test limits and content during production testing on-the-fly. Adaptive testing[16],[17] is now being advocated, by dropping unnecessary test items to reduce the test costs, or by heightening test limit criteria to improve the test quality. Unlike conventional test, all test items do not require thorough testing, it considers whether these test items are effective based on the test outcomes of the sample dies, and adaptive testing selects only the most effective test items.…”

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confidence: 99%

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Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm

Song

Liang

et al. 2020

IEEE Access

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With the growing complexity of integrated circuits (IC), more and more test patterns are added to test set to test more defects, making the number of test pattern and individual test pattern length continues to increase as the size of IC gets larger, boosting test time and consequently test cost. To solve this problem, this paper proposes a kind of valid pattern identification method. The method uses machine learning to reorder the test pattern which can select the most effective patterns, to determine the optimal training set and test set first. Then, by means of the weighted SVMRANK algorithm to find the optimal pattern sequence. Experiment results demonstrate that the method only sacrifices 2% prediction accuracy in exchange for 3.89 times the time saving. The method aims at maximizing the accuracy of test, and minimizing the number of patterns. The proposed idea significantly improves the test time and test efficiency compared to conventional test flows. This is an innovative test cost reduction method with the growing complexity of IC. INDEX TERMS Adaptive test, machine learning, test reorder.

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Section: The Last Column Ofmentioning

confidence: 93%

Section: Enormous Defect Detection Overlap Problem Between Test Typesmentioning

confidence: 99%

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confidence: 99%

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Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm

Song

Liang

et al. 2020

IEEE Access

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“…For these, the performance of the classification algorithm is limited unless a higher computational cost is paid. The outlier detection algorithm performs better in this regard [1], and better results may be obtained through weighted combination.…”

Section: Threshold Of Prediction Modelmentioning

confidence: 97%

“…As the scaling of ICs (integrated circuits) continues, more advanced and complex structures demand comprehensive tests [1]. This results in a significant increase in test costs to ensure high test quality (fewer test escapes).…”

Section: Introductionmentioning

confidence: 99%

Identifying the Optimal Subsets of Test Items through Adaptive Test for Cost Reduction of ICs

et al. 2021

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With the growing complexity of integrated circuits (ICs), more and more test items are required in testing. However, the large number of invalid items (which narrowly pass the test) continues to increase the test time and, consequently, test costs. Aiming to address the problems of long test time and reduced test item efficiency, this paper presents a method which combines a fast correlation-based filter (FCBF) and a weighted naive Bayesian model which can identify the most effective items and make accurate quality predictions. Experimental results demonstrate that the proposed method reduces test time by around 2.59% and leads to fewer test escapes compared with the recently adopted test methods. The study shows that the proposed method can effectively reduce the test cost without jeopardizing test quality excessively.

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