Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm

Song, Tai; Liang, Hongbin; Ni, Tianming; Huang, Zhengfeng; Lu, Yingchun; Wan, Jinlei; Yan, Aibin

doi:10.1109/access.2020.3016039

Cited by 13 publications

(4 citation statements)

References 20 publications

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“…In order to achieve the biggest time savings, adaptive test reorder the test item as is shown in the right part in Fig. 1, rank forward the item which are most likely to fail, and the most effective test item can be executed first [29].…”

Section: Preliminariesmentioning

confidence: 99%

“…Some irrelevant or redundant test patterns exist in the increased test set, and the effectiveness of the test pattern is reduced [5]. New test types such as N-detect [6] and gate-exhaustive tests [7] further exacerbate the issue by systematically adding redundancy into the test set in order to increase the probability of detection of actual silicon defects.…”

Section: Introductionmentioning

confidence: 99%

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Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs

Song

Liang

Huang

et al. 2021

IEICE Electron. Express

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With the continuous drive toward integrated circuits (ICs) scaling, more test patterns are required in testing. However, the large number of patterns continues to increase test time and test costs. Thus, test costs of ICs are becoming more crucial yet more challenging. In this paper, we propose a novel adaptive test strategy to reduce test costs without increasing test escape, and using shortest path first (SPF) algorithm combined with K-Nearest Neighbor (KNN) to reorder the test patterns. The patterns which identify faults earlier are moved forward and applied first so as to save test time. In addition, the optimal test patterns are searched by means of a polynomial regression function and it provides a trade-off between test cost and test escape. Consequently, the optimization problem is converted into a mathematical function, in order to achieve broader applicability and generality. Experimental results demonstrate that the proposed method achieved 54.2 seconds time savings but leads to almost negligible test escapes increasing compared with traditional methods. The test pattern reordering method aims to find defects as early as possible. Furthermore, the proposed algorithm is completely software based and incurs no additional hardware overhead.

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Section: Preliminariesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs

Song

Liang

Huang

et al. 2021

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

show abstract

“…However, this method is limited by the online computation overhead. The research in this part focuses on how to design the pipelined test methodology [6,26] of ATE and develop efficient incremental learning methods [27,28]. This is an issue worth studying in future work.…”

Section: Comparison Of Different Wafersmentioning

confidence: 99%

“…The higher the number of test items, the higher the number of irrelevant or redundant ones, thereby reducing the effectiveness of the test items [5]. Chips coming from the same fabs, the same batch or the same flow may share similar defects [6]. Therefore, it is unnecessary to use the full items for testing; the most appropriate method is to select a subset of specification parameters to measure and achieve an acceptable defect level [7].…”

Section: Introductionmentioning

confidence: 99%

Identifying the Optimal Subsets of Test Items through Adaptive Test for Cost Reduction of ICs

et al. 2021

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With the growing complexity of integrated circuits (ICs), more and more test items are required in testing. However, the large number of invalid items (which narrowly pass the test) continues to increase the test time and, consequently, test costs. Aiming to address the problems of long test time and reduced test item efficiency, this paper presents a method which combines a fast correlation-based filter (FCBF) and a weighted naive Bayesian model which can identify the most effective items and make accurate quality predictions. Experimental results demonstrate that the proposed method reduces test time by around 2.59% and leads to fewer test escapes compared with the recently adopted test methods. The study shows that the proposed method can effectively reduce the test cost without jeopardizing test quality excessively.

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