Algorithmic-Level Approximate Tensorial SVM Using High-Level Synthesis on FPGA

Younes, Hamoud; Ibrahim, Alì; Rizk, Mostafa; Valle, Maurizio

doi:10.3390/electronics10020205

Cited by 18 publications

(8 citation statements)

References 21 publications

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“…In this paper, the kNN algorithm is adopted for the design of an embedded tactile data processing architecture due to the: 1) high level of parallelization of the kNN algorithm, which makes it adequate for hardware acceleration, 2) high classification accuracy with a reduced computational complexity compared to state-of-the-art algorithms operating on the same task [28], [29], and 3) ability of complexity reduction without affecting the application quality using approximate computing techniques [23].…”

Section: Selection-based Knn Implementation and Case Studymentioning

confidence: 99%

An Efficient Selection-Based kNN Architecture for Smart Embedded Hardware Accelerators

Younes¹,

Ibrahim

Rizk

et al. 2021

IEEE Open J. Circuits Syst.

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K-Nearest Neighbor (kNN) is an efficient algorithm used in many applications e.g. text categorization, data mining, and predictive analysis. Despite having a high computational complexity, kNN is a candidate for hardware acceleration since it is a parallelizable algorithm. This paper presents an efficient novel architecture and implementation for a kNN hardware accelerator targeting modern System-on-Chips (SoCs). The architecture adopts a selection-based sorter dedicated for kNN that outperforms traditional sorters in terms of hardware resources, time latency, and energy efficiency. The kNN architecture has been designed using High-Level Synthesis (HLS) and implemented on the Xilinx Zynqberry platform. Compared to similar state-of-the-art implementations, the proposed kNN provides speedups between 1.4× and 875× with 41% to 94% reductions in energy consumption. To further enhance the proposed architecture, algorithmic-level Approximate Computing Techniques (ACTs) have been applied. The proposed approximate kNN implementation accelerates the classification process by 2.3× with an average reduced area size of 56% for a real-time tactile data processing case study. The approximate kNN consumes 69% less energy with an accuracy loss of less than 3% when compared to the proposed Exact kNN.

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Section: Selection-based Knn Implementation and Case Studymentioning

confidence: 99%

An Efficient Selection-Based kNN Architecture for Smart Embedded Hardware Accelerators

Younes¹,

Ibrahim

Rizk

et al. 2021

IEEE Open J. Circuits Syst.

Self Cite

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“…Several subsequent works applied different techniques on the same dataset to improve generalization performance and reduce computational costs. In [12], [13], the authors adopted the k-NN and the SVM models to address a two-class classification problem; approximate computing techniques reduced the execution time and memory usage during the inference phase.…”

Section: Related Workmentioning

confidence: 99%

1-D Convolutional Neural Networks for Touch Modalities Classification

Gianoglio

Ragusa

Zunino

et al. 2021

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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Artificial tactile systems can facilitate the life of people suffering from a loss of the sense of touch. These systems use sensors and digital, battery-operated embedded units for data processing. Therefore, low-power, resource-constrained devices should host those embedded devices. The paper presents a framework based on 1-D convolutional neural networks (CNNs), which tackles the problem of classifying touch modalities, while limiting the number of architecture parameters. The paper also considers the computational cost of the pre-processing stage that handles tactile-sensor data before classification. The related pre-processing unit affects resources occupancy, computational cost, and ultimately classification accuracy. The experimental session involved a state-of-the-art real-world dataset containing three touch modalities. The 1-D CNN outperformed existing solutions in terms of accuracy, and showed a satisfactory trade-off between accuracy, computational cost, and resources occupancy. The implementation of the 1-D CNN classifier on an Arduino Nano 33 BLE device yielded real-time performances.

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“…The design input of hardware also must be software instead of the hardware description language to implement different NPR hardware modules flexibly and quickly. So, we have proposed a smart glass with a field programmable gate array, FPGA, and are developing an NPR library that can be converted to efficient hardware automatically by high-level synthesis (2)(3)(4) . To our best knowledge, there is no research about such smart glass and the HLS-oriented NPR library.…”

Section: Introductionmentioning

confidence: 99%

Process Chaining Without Image and Performance Loss for Pencil Drawing Style Image Conversion in High-Level Synthesis

Tani,

Yamawaki

2023

The Proceedings of the 10th International Conference on Intelligent Systems and Image Processing 2023

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We are developing high-performance and low-power non-photorealistic rendering hardware for an embedded image processing system using High-Level Synthesis (HLS) technology, which automatically converts software to hardware. The hardware of pencil drawing style image conversion, which is one of NPRs, has been studied as a first step. To make HLS generate a well-pipelined hardware module with burst transfer, we have applied the memory access streaming technique for window-level processing. However, this technique has a weak point that lacks the upper and left side edges of the input image while the ideal performance can be achieved. This paper develops HLSoriented software for the pencil drawing style conversion, which can compensate for the shaved image without affecting the performance. The experimental result shows that our proposal can obtain the output image without any lack. In addition, the effects lead by our extension to the execution time, hardware resource, and power efficiency are little.

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Algorithmic-Level Approximate Tensorial SVM Using High-Level Synthesis on FPGA

Cited by 18 publications

References 21 publications

An Efficient Selection-Based kNN Architecture for Smart Embedded Hardware Accelerators

An Efficient Selection-Based kNN Architecture for Smart Embedded Hardware Accelerators

1-D Convolutional Neural Networks for Touch Modalities Classification

Process Chaining Without Image and Performance Loss for Pencil Drawing Style Image Conversion in High-Level Synthesis

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