“…Power consumption in FIR filters can be minimized by reducing hardware complexity through filter implementation architecture (Arslan et al, 1996;Azarmehr and Ahmadi, 2012;Su et al, 1994;Mehendale et al, 1998;Hong et al, 2002;Xie et al, 2010) or by reducing switching activities between filter coefficients (Kavitha and Sasikumar, 2014;Najm, 1993;Nemani and Najm, 1996;Rahmeier et al, 2013;Shao et al, 2006) in their binary form, while processing through data buses of FPGA. In existing literature, Hamming distance (HD) between successive coefficients (Aktan et al, 2008;Gustafsson and Wanhammar, 2002;Mehendale et al, 1995;Merakos et al, 1997;Sankarayya et al, 1997) has been considered as a measure of switching activity. In other words, power consumption reduction in filter execution has been achieved by reducing the HD between the coefficients of the designed filter.…”