Algorithms for optimizing, two-dimensional symbolic layout compaction

Wolf, Wayne; Mathews, Robert G.; Newkirk, John A.; Dutton, R.W.

doi:10.1109/43.3180

Cited by 15 publications

(2 citation statements)

References 19 publications

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“…The idea of breaking the longest path in the constraint graph is not new. The vertex splitting idea has been proposed before but only used as a heuristic to break the critical path iteratively without a systematic method to manipulate the jogs [39] and as a result, it need not necessarily produce an optimal solution. Our main contribution is to provide a systematic method to introduce jogs breaking the longest path and obtaining an optimal width after compaction.…”

Section: Nonhorizontal Wiresmentioning

confidence: 99%

A Faster One-Dimensional Topological Compaction Algorithm with Jog Insertion

Chen

Lee

2000

Algorithmica

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We consider the problem of one-dimensional topological compaction with jog insertions. By combining both geometric and graph-theoretic approaches we present a faster and simpler algorithm to improve over previous results. The compaction algorithm takes as input a sketch consisting of a set F of features and a set W of wires, and minimizes the horizontal width of the sketch while maintaining its routability. The algorithm consists of the following steps: constructing a horizontal constraint graph, computing all possible jog positions, computing the critical path, relocating the features, and reconstructing a new sketch homotopic to the input sketch, which is suitable for detailed routing. The algorithm runs in O(|F| · |W |) worst-case time and space, which is asymptotically optimal in the worst case. Experimental results are also presented.

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Section: Nonhorizontal Wiresmentioning

confidence: 99%

A Faster One-Dimensional Topological Compaction Algorithm with Jog Insertion

Chen

Lee

2000

Algorithmica

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“…To achieve the compacted layout with only one operation is the aim of 2-dimensional compaction. Some of those algorithms [4] [5] had been reported.…”

Section: Introductionmentioning

confidence: 97%

An efficient two-dimensional compaction algorithm for VLSI symbolic layout

Wei¹,

Leroy²,

Crappe³

Proceedings of the European Design Automation Conference, 1990., EDAC.

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The 2-dimensional compaction problem for VLSI symbolic layout is considered. Through carefully arranging the constraints among the elements which are represented as rectangles and h e compaction strategies including the basic 2-dimensional compaction and the jog, the goal to compact the layout so that its bounding rectangle has a minimum or an approximately minimum area, is achieved. A systematical search method is mmmended to find the proper jog points on the wires. A reversed compaction is used to optimize the compacted result. The procedure of designers' work is fully considered in or& to accelerate the Compacting pocess.

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Geometric approach to VLSI layout compaction

Xiong¹,

Kuh

1990

Circuit Theory & Apps

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SUMMARYWe present a new geometric approach to VLSI layout compaction in this paper. In contrast to existing compaction algorithms, we rely on the geometric method and bypass both compaction grids and constraint graphs during the entire compaction process.A systematic and efficient way is introduced to enumerate all possible jogs. For the given layout topology we prove that the geometric algorithm yields the minimum-area layout in one-dimensional compaction with automatic jog insertion. In the final output, only necessary jogs are inserted and the total wire length is minimized as a secondary goal. Furthermore, the integration of local compaction tools into a layout CAD system and the practical extensions of our algorithm are addressed.

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Algorithms for optimizing, two-dimensional symbolic layout compaction

Cited by 15 publications

References 19 publications

A Faster One-Dimensional Topological Compaction Algorithm with Jog Insertion

A Faster One-Dimensional Topological Compaction Algorithm with Jog Insertion

An efficient two-dimensional compaction algorithm for VLSI symbolic layout

Geometric approach to VLSI layout compaction

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