Geometric approach to VLSI layout compaction

Xiong, Xiao-Ming; Kuh, E.S.

doi:10.1002/cta.4490180408

Cited by 4 publications

(2 citation statements)

References 28 publications

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“…(3) The layout is compacted, first vertically and then horizontally. The compaction algorithm is a simplified version of the one-dimensional channel compaction algorithm presented in Xiong and Kuh [1996] which adapts a scan-line approach. Area and aspect ratio of the layout is now computed.…”

Section: Solution Representation and Decodermentioning

confidence: 99%

A performance-driven IC/MCM placement algorithm featuring explicit design space exploration

Esbensen

Kuh

1997

ACM Trans. Des. Autom. Electron. Syst.

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A genetic algorithm for building-block placement of ICs and MCMs is presented that simultaneously minimizes layout area and an Elmore-based estimate of the maximum path delay while trying to meet a target aspect ratio. Explicit design space exploration is performed by using a vector-valued, 3-dimensional cost function and searching for a set of distinct solutions representing the best trade-offs of the cost dimensions. From the output solutions, the designer can choose the solution with the preferred trade-off. In contrast to existing approaches, the required properties of the output solutions are specified without using weights or bounds. Consequently, the practical problems of specifying these quantities are eliminated. Promising experimental results are obtained for various placement problems, including a real-world design. Solution sets representing good, balanced cost trade-offs are found using a reasonable amount of runtime. Furthermore, the performance is shown to be comparable to that of simulated annealing in the special case of 1-dimensional optimization, in which direct comparison is possible.

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Section: Solution Representation and Decodermentioning

confidence: 99%

A performance-driven IC/MCM placement algorithm featuring explicit design space exploration

Esbensen

Kuh

1997

ACM Trans. Des. Autom. Electron. Syst.

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“…In contrast to existing compaction algorithms, a new geometric approach to VLSI layout compaction is discussed in Ref. [2], which yields the minimum area layout in one-dimensional compaction with automatic jog insertion. The efficiency of these operations substantially depends on the data structures adopted.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis

Bhuvaneswari

Prasad

Singh

et al. 2011

Circuit Theory & Apps

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SUMMARYBinary decision diagrams (BDDs) are the most frequently used data structure for the representation and handling of Boolean functions because of their excellent time and space efficiencies. In this article, a reversed BDD-based pass transistor logic (PTL) logic synthesis is presented for low-power and high-performance circuits without exploiting the canonical property of BDDs. The procedure of the reversed BDD transformation into PTL is achieved by a one-to-one correspondence with the BDD node and PTL cell. Layouts are generated for the benchmark circuits and simulated in terms of power dissipation, propagation delay and area. The reversed BDD technique performs better in terms of area, delay and power dissipation due to the regularity, a reduced critical path, less interconnection wires, a multiplexer-based construction of PTL circuits, and less switching activities.

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