All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme

Abstract

This paper proposes a 90°phase-shift delay-locked loop (DLL) used in dynamic RAM for data sampling clock generation. The proposed DLL alleviates process variation issues, which are mainly caused by the mismatch between the delay line segments in the previous 90°phase-shift DLLs, and reduces area by adopting a multiplying DLL-based structure. In addition, a novel jitter suppression scheme is also proposed to suppress control code dithering. A stochastic analysis is performed to evaluate the effectiveness of the proposed dithering jitter suppression. The proposed DLL is fabricated using a 45-nm CMOS process on an active area of 69.9 µm × 49.3 µm and utilizes a 1.1 V supply voltage. The proposed DLL has an operating frequency ranging from 500 to 800 MHz and consumes 1.32 mW at 800 MHz. The measured rms and peak-to-peak output jitters are improved by 5.42% to 18.75% and 5.52% to 18.31%, respectively, in the entire operating frequency range.Index Terms-90°phase shift, delay-locked loops (DLLs), dithering jitter suppression, dynamic RAM (DRAM), low jitter.

A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor

“…To overcome the limitation of TSDPD, dithering suppression loop controller (DSLC) is proposed in [16] as shown in the Fig. 2 (d).…”

An area-efficient and wide-range digital DLL for per-pin deskew applications

“…However, achieving high-frequency operation is difficult because of the requirement for frequency multiplication. In addition, conventional DLLs [2][3][4]6,8,[10][11][12][13][14] only consider the design of the 90 • phase shifter; per-pin deskew is not supported in these DLLs.…”

“…With increasing operating frequency, the duty cycle distortion, the reference clock jitter, and the pin-topin delay mismatch adversely affect the valid sampling window. A delay-locked loop (DLL) is often used to achieve a high-quality phase shift or phase alignment for the sampling clock [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. In practice, the routing difference and the different path characteristics of the parallel pins cause considerable pin-to-pin delay mismatch [7].…”

“…A small phase shift cannot be obtained via directly downscaling the control code of the main delay line in the DLL. Thus, a multiplying DLL-based structure [13] has been proposed to overcome the mismatch among the equal delay units, and the clock signal at twice the operating frequency is divided by a frequency divider to provide a 90 • phase shift. However, achieving high-frequency operation is difficult because of the requirement for frequency multiplication.…”