All-Digital Background Calibration of a Successive Approximation ADC Using the “Split ADC” Architecture

McNeill, John; Chan, Ka Yan; Coln, Michael C. W.; David, Christopher; Brenneman, Cody R.

doi:10.1109/tcsi.2011.2123590

Cited by 97 publications

(49 citation statements)

References 7 publications

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“…In this section, we analyze the effect of capacitor variation on the two inequalities, i.e., (3) and (6).…”

Section: B Accounting For Capacitor Variationmentioning

confidence: 99%

“…Analog calibrations using additional digital-to-analog converters (DACs) were proposed in the 1980s [4], [5]. Recently, more efforts [6]- [8] have been made to push calibration into the digital domain since the scaling of CMOS technology offers advantages of digital circuitry in terms of speed, power, and integration.…”

mentioning

confidence: 99%

“…Split-ADC equalization [6] implements two identical ADCs on the same chip, captures the difference between their outputs, and simultaneously calibrates their bit weights until the captured difference is minimized. To simplify this technique, a selfequalization approach [7] works on a single ADC by em- ploying an offset double conversion scheme.…”

mentioning

confidence: 99%

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Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs

Zhang

Alvandpour

2014

IEEE Trans. Circuits Syst. II

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Abstract-This brief analyzes the effect of capacitor variation on the design of high-resolution nonbinary-weighted successiveapproximation-register analog-to-digital converters in terms of radix, conversion steps, and accuracy. Moreover, the limitation caused by the one-side redundancy of the nonbinary-weighted network is addressed and a corresponding solution with a mathematical derivation is provided. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity, a bottom-up weight calibration technique accounting for noise and offset errors is proposed, and its effectiveness is demonstrated. This calibration approach can be easily incorporated into a charge-redistribution converter without modifying its main architecture and conversion sequence.Index Terms-Capacitor variation, digital error correction, nonbinary weighted, redundancy, successive approximation, successive approximation register (SAR) analog-to-digital converters (ADCs), weight calibration.

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“…In this section, we analyze the effect of capacitor variation on the two inequalities, i.e., (3) and (6).…”

Section: B Accounting For Capacitor Variationmentioning

confidence: 99%

mentioning

confidence: 99%

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Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs

Zhang

Alvandpour

2014

IEEE Trans. Circuits Syst. II

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“…In [1], the "split ADC" architecture is applied to SAR ADC to correct the capacitor mismatch error. A perturbation-based background digital calibration is proposed in [2].…”

Section: Introductionmentioning

confidence: 99%

“…Dithering technique is developed in [3] to examine the MSB capacitor weights. The main drawbacks of the above calibration methods are that an additional ADC is required [1] or the input signal range is reduced due to the injected offset [2] or dither signals [3].…”

Section: Introductionmentioning

confidence: 99%

A digital background calibration technique for SAR ADC based on capacitor swapping

Ning

et al. 2014

IEICE Electron. Express

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A digital background calibration technique that compensates for capacitor mismatches is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in the SAR ADC based on tri-level switching. The termination capacitor in the digital-to-analog converter is considered as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation result shows that the signal-to-noise and distortion ratio is improved from 57.1 dB to 72.0 dB and the spurious free dynamic range is improved from 62.0 dB to 82.6 dB.

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LMS-Based Background Calibration of Bit Weights in SAR ADC Using Reinforcement Learning Optimization

Song,

Meng,

Huang

et al. 2023

Circuits Syst Signal Process

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All-Digital Background Calibration of a Successive Approximation ADC Using the “Split ADC” Architecture

Cited by 97 publications

References 7 publications

Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs

Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs

A digital background calibration technique for SAR ADC based on capacitor swapping

LMS-Based Background Calibration of Bit Weights in SAR ADC Using Reinforcement Learning Optimization

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