All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition

Duc, Han Le; Nguyen, Duc Minh; Jabbour, Chadi; Graba, Tarik; Desgreys, Patricia; Jamin, Olivier; Nguyen, Van Tam

doi:10.1109/tcsii.2015.2483423

Cited by 58 publications

(9 citation statements)

References 14 publications

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“…Taking the advantages of CMOS scaling and portability between technology nodes, all-digital calibration techniques eliminate the above analog and mixed-signal issues [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31]. These techniques often focus on one or two types of mismatches among the gain and timing mismatches, without the offset mismatch [13][14][15][16][17][18][19][20][21][22][23][24][25]. The authors in [30] proposed a technique to calibrate all of three above mismatches.…”

Section: U Xmentioning

confidence: 99%

“…Some of these perform the channel mismatch calibration in either the all-analog domain or mixed-signal domain [7][8][9][10][11][12]. The all-analog calibration techniques have the drawbacks of very complicated analog estimation circuits, low accuracy, and CMOS technology unsuitability [13]. On the other hand, the mixed-signal calibration techniques require low power consumption and small chip area.…”

Section: Introductionmentioning

confidence: 99%

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An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Hoang

Pham

et al. 2020

Electronics

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The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.

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Section: U Xmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Hoang

Pham

et al. 2020

Electronics

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“…From (12), it can be seen that the TIADC output y(n) can be generated by feeding the input signal x(n) through an Mperiodic time-varying polynomial function…”

Section: System Modelmentioning

confidence: 99%

“…Unfortunately, the non-ideal effects in the analog building block implementations cause significant performance degradation for TIADC system [6,7]. During the past few decades, the estimation and compensation methods for offset, gain, time, and frequency mismatches are investigated extensively [8][9][10][11][12][13]. In recent years, there has been an increasing interest in nonlinear mismatch problems in TIADC system [14][15][16][17][18][19][20][21][22][23][24][25].…”

Section: Introductionmentioning

confidence: 99%

Calibration of static nonlinearity mismatch errors in TIADC based on periodic time-varying adaptive method

Wei

Zhang

et al. 2020

IEICE Electron. Express

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The nonlinear behaviors of time-interleaved analog-to-digital converter (TIADC) caused by non-ideal circuit implementations degrade performance of TIADC significantly. This paper proposes a calibration method based on model inversion strategy to compensate for static nonlinearities in TIADC, since static nonlinearities are the major compositions of the nonlinear behaviors in most situations. The proposed periodic time-varying adaptive calibration method can estimate coefficients of inverse polynomial model directly and capture variations of the nonlinear parameters when environment changes. The method proposed in this paper is also applicable to dynamic nonlinearities by changing polynomial with Volterra series. Simulation results show the effectiveness and robustness of the proposed method.

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“…H. Le Duc et al extended this technique to all NBs with relaxed constraints on input, by adding a Hilbert filter on the basis of the derivative filter [26,28]. Later, they eliminated the limit on the number of sub-ADC channels [32,33]. However, the calibration techniques proposed in [32] and [33] also have a couple of limitations: (1) When implemented in an FPGA, a considerable amount of DSPs are wasted as these techniques are not specifically optimized for DSPs.…”

mentioning

confidence: 99%

Low computing resource consumption fully digital foreground calibration technique for time-interleaved analog-to-digital converter

Cao

Liu

et al. 2020

J. Inst.

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A time-interleaved analog-to-digital converter (TI-ADC) uses several sub-analog-todigital converters (sub-ADCs) to achieve a high sampling rate. Its applications include communication systems, oscilloscopes, healthcare instruments, etc. However, the presence of sub-ADC channel mismatches such as offset, gain and sample-time mismatches can significantly degrade the performance of TI-ADCs. This paper proposes a fully digital foreground calibration technique for the TI-ADC, including mismatch correction and estimation blocks. Unlike existing techniques, the proposed technique requires low computational resources. As the resource for complex computing in a field-programmable gate array (FPGA) is mainly the digital signal processor (DSP), the mismatch correction block unifies each computing unit in the FPGA into a multiply adder to achieve low DSP consumption. To further reduce the use of DSP resources, the selection of an optimal number of taps of the finite impulse response filter used for mismatch correction is discussed. The optimal-tap filter that uses the lowest amount of DSPs while satisfying the required signal-to-noise and distortion ratio flat area bandwidth is presented. A real-time hardware correction block was implemented for an 8 Gs/s TI-ADC system with two sub-ADC channels, and the results with this hardware verify the low computing resource consumption feature of the proposed calibration technique.

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All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition

Cited by 58 publications

References 14 publications

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Calibration of static nonlinearity mismatch errors in TIADC based on periodic time-varying adaptive method

Low computing resource consumption fully digital foreground calibration technique for time-interleaved analog-to-digital converter

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