All‐digital synchronous 2 × time‐difference amplifier based on time register

Abstract

A novel 2 × time-difference amplifier (TDA) in 65 nm CMOS technology is presented. Unlike traditional analogue TDA, the proposed TDA, employing an all-digital synchronous architecture, achieves 2 × TDA in a time subtracting way based on time register. Multi-path negative skewed gated delay cells are utilised to minimise gating skew error in the time register. To make up for the delay mismatch in the two time registers, a foreground calibration scheme that calibrates the input offset of the phase detectors at the same time is applied. The TDA gain ranges from 1.99 to 2.02 over ± 150 ps input time-difference range and the standard variation of the gain is 0.02 under various process, voltage and temperature (PVT) conditions. The simulated average of power consumption is 62 μW under 100 MHz clock frequency.

Process and temperature robust time‐difference amplifier with analog calibration

“…The use of the TA within the TDC depends on the input TA dynamic range, linearity, and gain. A TA can amplify a time difference based on the Set-Reset (SR) latch meta-stability [6], all-digital approaches [7], or cross-coupled structures. In cross-coupled structures, the TA output nodes are discharged by two branches whose control voltages (and therefore discharge current) depend on the opposite output nodes and a replica branch [8].…”