A high-precision time integrator is presented whose output is the accumulation of sequence of time inputs. A novel time adder with time-domain differential structure is proposed to avoid commonmode errors such as supply noise and leakage current. The performance under various process, voltage and temperature conditions is examined in detail. By using two time adders in parallel, a differential synchronous time integrator is proposed, which is easier to cascade with other time-mode arithmetic circuit. Implemented in 65 nm 1.2 V CMOS technology, the proposed time integrator achieves a gain of 27.97 dB with a 317 kHz 30 ps peak-to-peak sinusoidal input, and consumes 152.7 mW with 50 MHz sampling rate. The experimental results confirm the integration operation is realised properly and accurately.

A novel 2 × time-difference amplifier (TDA) in 65 nm CMOS technology is presented. Unlike traditional analogue TDA, the proposed TDA, employing an all-digital synchronous architecture, achieves 2 × TDA in a time subtracting way based on time register. Multi-path negative skewed gated delay cells are utilised to minimise gating skew error in the time register. To make up for the delay mismatch in the two time registers, a foreground calibration scheme that calibrates the input offset of the phase detectors at the same time is applied. The TDA gain ranges from 1.99 to 2.02 over ± 150 ps input time-difference range and the standard variation of the gain is 0.02 under various process, voltage and temperature (PVT) conditions. The simulated average of power consumption is 62 μW under 100 MHz clock frequency.

No abstract