Proceedings of the 2004 International Symposium on Physical Design 2004
DOI: 10.1145/981066.981069
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Almost optimum placement legalization by minimum cost flow and dynamic programming

Abstract: VLSI placement tools usually work in two steps: First, the cells that have to be placed are roughly spread out over the chip area ignoring disjointness (global placement). Then, in a second step, the cells are moved to their final position such that all overlaps are removed and all additional constraints are met (detailed placement or legalization).We consider algorithms for legalization. In particular, we analyze a generic legalization algorithm based on minimum cost flows and dynamic programming. Specializat… Show more

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Cited by 53 publications
(30 citation statements)
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“…Experimental results show that the gap between a computed solution and a theoretical lower bound is only approximately 10%, and neither timing nor routability is significantly affected [6].…”
Section: Detailed Placementmentioning
confidence: 95%
“…Experimental results show that the gap between a computed solution and a theoretical lower bound is only approximately 10%, and neither timing nor routability is significantly affected [6].…”
Section: Detailed Placementmentioning
confidence: 95%
“…Instead, it directly alters the quadraticwirelength objective to minimize the sum of all cells' displacements from their assigned subregions. The following four steps are then repeated until subregions become small enough that legalization and detailed placement by local perturbations can be applied [Brenner et al 2004].…”
Section: Partitions Guided By Analyticalmentioning
confidence: 99%
“…This observation has renewed interest in improved methods for legalization [Li and Koh 2003;Agnihotri et al 2003;Khatkhate et al 2004] and detailed placement [Brenner et al 2004;Ramachandaran et al 2005]. Nevertheless, progress in global placement still continues to be made.…”
Section: Legalization and Detailed Placementmentioning
confidence: 99%
“…A number of recent publications address precisely the issue of stability in physical synthesis optimizations. For example, Li et al [21] propose an incremental placement algorithm which maintains the stability of placement for gate sizing and buffer insertion, while Luo et al [24] and Brenner et al [4] address this same problem by designing legalizer tools that seek to preserve performance metrics. However, these approaches tend to break down in later stages of physical design, when circuits are heavily optimized.…”
Section: Introductionmentioning
confidence: 99%