High sampling speed can be achieved using multiple Analog-to-Digital Converters (ADCs) based on the Time-Interleaving A/D Conversion (TIADC) technique. Various types of methods were proposed to correct the mismatch errors among parallel ADC channels in TIADC systems, which would deteriorate the system performance. Traditional correction methods based on digital signal processing have good performance, however often only for input signals limited in a narrow frequency band. In this paper, we present our recent work on design of an 8-Gsps 12-bit TIADC system and implementation of real-time mismatch correction algorithms in FPGA devices, over a broad band of input signal frequencies. Tests were also conducted to evaluate the systems performance, and the results indicate that the Effective Number of Bits (ENOB) is enhanced to be better than 8.5 bits (<800 MHz) and 8 bits from 800 MHz to 1.6 GHz after correction, almost the same with that of the ADC chip employed. Index Terms-time-interleaved technique, high-speed high-resolution A/D conversion, mismatch errors, real-time correction algorithms, broad band. I. INTRODUCTION AVEFORM digitization is a preferable solution in physics to obtain the most detailed information from the signals out of detectors, and has thus been employed in many physics experiments [1]-[11]. With the development of electronics, especially ASIC design on Analog-to-Digital Converters (ADCs), sampling speed has been increasing. With the Time Interleaved A/D Conversion (TIADC) technique, the system sampling speed can be greatly enhanced beyond single ADC ASIC's capability [8]-[10], which makes the study in this direction a research hot spot.