2018
DOI: 10.1109/tns.2018.2878875
|View full text |Cite
|
Sign up to set email alerts
|

An 8-Gs/s 12-Bit TIADC System With Real-Time Broadband Mismatch Error Correction

Abstract: High sampling speed can be achieved using multiple Analog-to-Digital Converters (ADCs) based on the Time-Interleaving A/D Conversion (TIADC) technique. Various types of methods were proposed to correct the mismatch errors among parallel ADC channels in TIADC systems, which would deteriorate the system performance. Traditional correction methods based on digital signal processing have good performance, however often only for input signals limited in a narrow frequency band. In this paper, we present our recent … Show more

Help me understand this report
View preprint versions

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1

Citation Types

0
3
0

Year Published

2020
2020
2023
2023

Publication Types

Select...
6

Relationship

0
6

Authors

Journals

citations
Cited by 13 publications
(3 citation statements)
references
References 31 publications
(20 reference statements)
0
3
0
Order By: Relevance
“…Foreground calibration involves offline mismatch estimation method to obtain mismatch parameters, and then designs the correction process based on these parameters. For instance, the perfect reconstruction (PR) [8,9] method utilizes the sine fitting method for calibration and then designs an FIR filter to filter the data. Background calibration, on the other hand, involves performing parameter calibration and system correction simultaneously during the sampling process.…”
Section: Jinst 18 P05024mentioning
confidence: 99%
“…Foreground calibration involves offline mismatch estimation method to obtain mismatch parameters, and then designs the correction process based on these parameters. For instance, the perfect reconstruction (PR) [8,9] method utilizes the sine fitting method for calibration and then designs an FIR filter to filter the data. Background calibration, on the other hand, involves performing parameter calibration and system correction simultaneously during the sampling process.…”
Section: Jinst 18 P05024mentioning
confidence: 99%
“…In the high-speed analog to digital conversion circuit, usually the phase-locked loop (PLL) is used to obtain a low phase noise so that the system can achieve a high signal-to-noise ratio (SNR) [17]. However, the disadvantage of the PLL is the large power dissipation.…”
Section: Data Acquisition Modulementioning
confidence: 99%
“…In TIADC systems, channel mismatches seriously degrade the signalto-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) [18,19,20,21,22,23,24,25,26,27,28,29]. In published literature, studies of TIADC are based on the effects of channel mismatches on the spectrum or dynamic performance such as SNDR and SFDR [14,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32]. Under the condition of large bandwidth, it is impossible to eliminate channel mismatches completely.…”
Section: Introductionmentioning
confidence: 99%