Alternative approaches to fault detection in FSMs

Leveugle, Régis; Rochet, R.; Saucier, G.

doi:10.1109/dftvs.1994.630040

Cited by 7 publications

(1 citation statement)

References 11 publications

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“…Besides, the error detection latency is nonzero. (An alternate approach has been reported in [14] where explicit signature adjustments are used instead of the state codes leading to implicit adjustments). For the self-monitoring technique in [7], the error detection latency can be made zero by choosing appropriate labels to generate the state codes.…”

Section: Inadequacy Of the Previous Methodsmentioning

confidence: 99%

Monitoring machine based synthesis technique for concurrent error detection in finite state machines

1996

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Abstract. This paper discusses a new design methodology for concurrent error detection in synchronous sequential circuits based on the use of monitoring machines. In this approach, an auxiliary sequential circuit, called the monitoring machine, operates in lock-step with the main machine, such that any fault in either of the two machines is immediately detected. This methodology is independent of the fault model. It can be applied to FSMs with pre-encoded states and can also be used for ones being synthesised. It also provides a systematic framework for the combined optimisation of the main and monitoring machines, and for exploring tradeoffs in their implementation.The design of monitored sequential circuits is a two-fold problem; namely one of designing an optimal monitoring machine given the main machine, and the other of encoding the main machine states so that the resulting monitoring machine is minimal. This paper formally discusses the design of both the main and monitoring machines and techniques for their combined optimisation. Tradeoffs in their implementation based on selective fault detection are also examined.Through experimental results, it is shown that the proposed synthesis technique is eminently suitable for the design of low-cost sequential circuits with concurrent error detection. The monitoring machine is less costly than the main machine. It is also not identical to it. As a result, a monitored sequential circuit has significantly lower hardware cost and improved fault coverage than previous implementations.

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Section: Inadequacy Of the Previous Methodsmentioning

confidence: 99%

Monitoring machine based synthesis technique for concurrent error detection in finite state machines

1996

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A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation

2005

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Efficiency comparison of signature monitoring schemes for FSMs

Rochet¹,

Leveugle²,

Saucier³

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 With EDA Technofair

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ISBN: 4930813670This paper addresses the detection of permanent and transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. Several Finite State Machine implementations using signature monitoring for control-flow checking are compared in terms of error detection latency, theoretical error coverage, experimental error coverage and area overheads. Advantages and drawbacks of each approach are presented

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Alternative approaches to fault detection in FSMs

Cited by 7 publications

References 11 publications

Monitoring machine based synthesis technique for concurrent error detection in finite state machines

Monitoring machine based synthesis technique for concurrent error detection in finite state machines

A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation

Efficiency comparison of signature monitoring schemes for FSMs

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